diff --git a/drivers/fpga_ip/Core10GBaseKR_PHY/Jenkinsfile b/drivers/fpga_ip/Core10GBaseKR_PHY/Jenkinsfile deleted file mode 100644 index 3f0f8f4..0000000 --- a/drivers/fpga_ip/Core10GBaseKR_PHY/Jenkinsfile +++ /dev/null @@ -1,2 +0,0 @@ -@Library('automated-testing-library') _ -pipelineSoftIPSrc() \ No newline at end of file diff --git a/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy.c b/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy.c index 25ed295..595b4a6 100644 --- a/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy.c +++ b/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy.c @@ -1,112 +1,116 @@ -#include "phy.h" +/** + * Copyright 2022 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * @file core10gbasekr_phy.c + * @author Microchip FPGA Embedded Systems Solutions + * @brief Core10GBaseKR_PHY Source + * + */ + +#include +#include "core10gbasekr_phy.h" #include "core10gbasekr_phy_link_training.h" /*------------------------Private Definitions---------------------------------*/ -#define AN_RESET (1U) -#define AN_ENABLE (1U) -#define AN_RESTART (1U) +#define AN_RESET (1U) +#define AN_ENABLE (1U) +#define AN_RESTART (1U) -#define TX_CTRL_DATA (0U) -#define TX_CTRL_AN (2U) -#define TX_CTRL_LT (3U) +#define TX_CTRL_DATA (0U) +#define TX_CTRL_AN (2U) +#define TX_CTRL_LT (3U) -/*------------------------Public Variables------------------------------------*/ -extern uint32_t prbs_cnt; +#define COEFF_UPDATE_PRESET (1U << 13U) +#define COEFF_UPDATE_INITIALIZE (1U << 12U) -/*------------------------Public Function-------------------------------------*/ - -/***************************************************************************//** - Please see phy.h for description - */ -void -PHY10GKR_init -( - phy10gkr_instance_t * this_phy, - addr_t base_addr -) -{ - /* Set Core10GBaseKR PHY Base addresses */ - this_phy->base_addr = base_addr; - this_phy->an_base_addr = this_phy->base_addr | C10GB_AN_BASE_OFFSET; - this_phy->lt_base_addr = this_phy->base_addr | C10GB_LT_BASE_OFFSET; - this_phy->tx_ctrl_base_addr = this_phy->base_addr | - C10GB_TX_CTRL_BASE_OFFSET; - this_phy->rx_status_base_addr = this_phy->base_addr | - C10GB_RX_STATUS_BASE_OFFSET; +#define MR_ADV_3_BIT_OFFSET (32U) +#define MR_ADV_FEC_ABILITY (46U) +#define MR_ADV_FEC_REQUESTED (47U) - PHY10GKR_config(this_phy); -} +/*------------------------Public Variables------------------------------------*/ +extern uint32_t prbs_cnt; -/***************************************************************************//** - Please see phy.h for description +/*------------------------Private Function-------------------------------------*/ +/** + * This is a private function which is called to reconfigure the core with + * default conditions, reset states, counters and algorithm attributes. */ -void -PHY10GKR_config -( - phy10gkr_instance_t * this_phy -) +static uint32_t +phy_10gbasekr_reset(phy10gkr_instance_t *this_phy) { /* set data path to AN block */ - HAL_set_32bit_reg_field(this_phy->tx_ctrl_base_addr, - C10GB_TX_CTRL_PMA_DATA, - TX_CTRL_AN); + HAL_set_32bit_reg_field(this_phy->tx_ctrl_base_addr, C10GB_TX_CTRL_PMA_DATA, TX_CTRL_AN); /* reset phy tx and rx */ - HAL_set_32bit_reg_field(this_phy->tx_ctrl_base_addr, - C10GB_TX_CTRL_TX_RESET, - 0x1); - HAL_set_32bit_reg_field(this_phy->tx_ctrl_base_addr, - C10GB_TX_CTRL_RX_RESET, - 0x1); + HAL_set_32bit_reg_field(this_phy->tx_ctrl_base_addr, C10GB_TX_CTRL_TX_RESET, 0x1); + HAL_set_32bit_reg_field(this_phy->tx_ctrl_base_addr, C10GB_TX_CTRL_RX_RESET, 0x1); /* set data path to AN block */ - HAL_set_32bit_reg_field(this_phy->tx_ctrl_base_addr, - C10GB_TX_CTRL_PMA_DATA, - TX_CTRL_AN); + HAL_set_32bit_reg_field(this_phy->tx_ctrl_base_addr, C10GB_TX_CTRL_PMA_DATA, TX_CTRL_AN); /* transmit equalization tap limit configurations */ + /* main coefficients (P0) */ HAL_set_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_MAX_MAIN_TAP, - C10GBKR_LT_MAIN_TAP_MAX_LIMIT); + this_phy->main_max_tap_ceoff); HAL_set_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_MIN_MAIN_TAP, - C10GBKR_LT_MAIN_TAP_MIN_LIMIT); + this_phy->main_min_tap_ceoff); + + if ((C10GBKR_LT_MAIN_TAP_MAX_LIMIT != this_phy->main_max_tap_ceoff)) + { + this_phy->main_preset_tap_coeff = this_phy->main_max_tap_ceoff; + } + /* post coefficients (P1) */ HAL_set_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_MAX_POST_TAP, - C10GBKR_LT_POST_TAP_MAX_LIMIT); + this_phy->post_max_tap_ceoff); HAL_set_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_MIN_POST_TAP, - C10GBKR_LT_POST_TAP_MIN_LIMIT); + this_phy->post_min_tap_ceoff); + + if ((C10GBKR_LT_POST_TAP_MAX_LIMIT != this_phy->post_max_tap_ceoff)) + { + this_phy->post_preset_tap_coeff = this_phy->post_max_tap_ceoff; + } + /* pre coefficients (P-1) */ HAL_set_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_MAX_PRE_TAP, - C10GBKR_LT_PRE_TAP_MAX_LIMIT); + this_phy->pre_max_tap_ceoff); HAL_set_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_MIN_PRE_TAP, - C10GBKR_LT_PRE_TAP_MIN_LIMIT); + this_phy->pre_min_tap_ceoff); - /* link partner preset conditions */ + if ((C10GBKR_LT_PRE_TAP_MAX_LIMIT != this_phy->pre_max_tap_ceoff)) + { + this_phy->pre_preset_tap_coeff = this_phy->pre_max_tap_ceoff; + } + + /* set core preset conditions */ HAL_set_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_PRESET_MAIN_TAP, - C10GBKR_LT_PRESET_MAIN_TAP); + this_phy->main_preset_tap_coeff); HAL_set_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_PRESET_POST_TAP, - C10GBKR_LT_PRESET_POST_TAP); + this_phy->post_preset_tap_coeff); HAL_set_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_PRESET_PRE_TAP, - C10GBKR_LT_PRESET_PRE_TAP); + this_phy->pre_preset_tap_coeff); - /* link partner preset conditions */ + /* set core initialize conditions */ HAL_set_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_INIT_MAIN_TAP, - C10GBKR_LT_INITIALIZE_MAIN_TAP); + this_phy->main_initialize_tap_coeff); HAL_set_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_INIT_POST_TAP, - C10GBKR_LT_INITIALIZE_POST_TAP); + this_phy->post_initialize_tap_coeff); HAL_set_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_INIT_PRE_TAP, - C10GBKR_LT_INITIALIZE_PRE_TAP); + this_phy->pre_initialize_tap_coeff); /* track number of fails since begining */ uint32_t tmp_fail_count = this_phy->lt.fail_cnt; @@ -115,9 +119,6 @@ PHY10GKR_config this_phy->lt.fail_cnt = tmp_fail_count; this_phy->lt.complete_cnt = tmp_complete_count; - /* set the request that will be sent to the link partner */ - this_phy->lt.rx_request = C10GBKR_LT_INITIAL_REQUEST; - /* Set AN and LT api state machine to init state */ this_phy->an.api_state = AN_API_SM_INIT; this_phy->lt.api_state = LT_API_SM_INIT; @@ -128,13 +129,13 @@ PHY10GKR_config /* clear link training tap data */ HAL_set_32bit_reg_field(this_phy->lt_base_addr, - C10GB_LT_LOCAL_RCVR_LOCKED, LOCAL_RXCVR_UNLOCKED); + C10GB_LT_LOCAL_RCVR_LOCKED, + LOCAL_RXCVR_UNLOCKED); this_phy->lt.local_rxcvr = LOCAL_RXCVR_UNLOCKED; - - this_phy->lt.main = (const phy10gkr_coeff_update_t) {0}; - this_phy->lt.post = (const phy10gkr_coeff_update_t) {0}; - this_phy->lt.pre = (const phy10gkr_coeff_update_t) {0}; + this_phy->lt.main = (const phy10gkr_coeff_update_t){0}; + this_phy->lt.post = (const phy10gkr_coeff_update_t){0}; + this_phy->lt.pre = (const phy10gkr_coeff_update_t){0}; this_phy->lt.lp_cal_sweep_state = MAIN_TAP; @@ -142,58 +143,93 @@ PHY10GKR_config this_phy->lt.rx_cal_cnt = 0; prbs_cnt = 0; + + return 0; } -/***************************************************************************//** - Please see phy.h for description +/** + * The private function enables the auto-negotiation state machine, this enables + * the auto-negotiation registers and then checks the status of the auto-negotiation + * state machine to determine if auto-negotiation has complete. */ -void -PHY10GKR_autonegotiate_sm -( - phy10gkr_instance_t * this_phy -) +static void +phy_10gbasekr_an(phy10gkr_instance_t *this_phy) { - switch(this_phy->an.api_state) + switch (this_phy->an.api_state) { case AN_API_SM_INIT: - /* Tx control: Auto-negotiation, PCS data transmitted to Serdes */ - HAL_set_32bit_reg_field(this_phy->tx_ctrl_base_addr, - C10GB_TX_CTRL_PMA_DATA, TX_CTRL_AN); + /* Reset auto-negotiation. */ + HAL_set_32bit_reg_field(this_phy->an_base_addr, C10GB_AN_RESET, AN_RESET); - /* set link fail inhibit timer time to 500 ms*/ - HAL_set_32bit_reg(this_phy->an_base_addr, - C10GB_AN_LINK_FAIL_INHIBIT_TIMER, - C10GBKR_AN_LINK_FAIL_INHITBIT_TIMER); + /* FEC configuration */ + this_phy->fec_negotiated = C10GBKR_FEC_NOT_NEGOTIATED; + ; - /* Reset auto-negotiation. */ - HAL_set_32bit_reg_field(this_phy->an_base_addr, - C10GB_AN_RESET, - AN_RESET); + uint32_t mr_adv_3 = + HAL_get_32bit_reg(this_phy->an_base_addr, C10GB_AN_MR_ADV_CAPABILITY_3); + + if (this_phy->fec_configured) + { + mr_adv_3 |= 1U << (MR_ADV_FEC_ABILITY - MR_ADV_3_BIT_OFFSET); + + if (this_phy->fec_request) + { + mr_adv_3 |= 1U << (MR_ADV_FEC_REQUESTED - MR_ADV_3_BIT_OFFSET); + } + } + else + { + /* clearing FEC bits */ + mr_adv_3 &= ~(1U << (MR_ADV_FEC_ABILITY - MR_ADV_3_BIT_OFFSET) | + 1U << (MR_ADV_FEC_REQUESTED - MR_ADV_3_BIT_OFFSET)); + } + HAL_set_32bit_reg(this_phy->an_base_addr, C10GB_AN_MR_ADV_CAPABILITY_3, mr_adv_3); /* Enable auto-negotiation. */ - HAL_set_32bit_reg_field(this_phy->an_base_addr, - C10GB_AN_ENABLE, - AN_ENABLE); + HAL_set_32bit_reg_field(this_phy->an_base_addr, C10GB_AN_ENABLE, AN_ENABLE); /* Restart auto-negotiation */ - HAL_set_32bit_reg_field(this_phy->an_base_addr, - C10GB_AN_RESTART, - AN_RESTART); + HAL_set_32bit_reg_field(this_phy->an_base_addr, C10GB_AN_RESTART, AN_RESTART); + + /* Tx control: Auto-negotiation, PCS data transmitted to Serdes */ + HAL_set_32bit_reg_field(this_phy->tx_ctrl_base_addr, + C10GB_TX_CTRL_PMA_DATA, + TX_CTRL_AN); + + /* set link fail inhibit timer time to 500 ms*/ + HAL_set_32bit_reg(this_phy->an_base_addr, + C10GB_AN_LINK_FAIL_INHIBIT_TIMER, + C10GBKR_AN_LINK_FAIL_INHITBIT_TIMER); + + this_phy->an.adv_ability = + (uint64_t)HAL_get_32bit_reg(this_phy->an_base_addr, C10GB_AN_MR_ADV_CAPABILITY_1) | + ((uint64_t)HAL_get_32bit_reg(this_phy->an_base_addr, C10GB_AN_MR_ADV_CAPABILITY_2) + << 16) | + ((uint64_t)HAL_get_32bit_reg(this_phy->an_base_addr, C10GB_AN_MR_ADV_CAPABILITY_3) + << 32); this_phy->an.status = STATUS_AN_INCOMPLETE; this_phy->an.api_state = AN_API_SM_STATUS_UPDATE; - break; + break; case AN_API_SM_STATUS_UPDATE: /* Get auto-negotiation state machine state */ - this_phy->an.state = HAL_get_32bit_reg_field(this_phy->an_base_addr, - C10GB_AN_STATE); - if(ST_AN_GOOD_CHECK == this_phy->an.state) + this_phy->an.state = HAL_get_32bit_reg_field(this_phy->an_base_addr, C10GB_AN_STATE); + if (ST_AN_GOOD_CHECK == this_phy->an.state) { this_phy->an.complete_cnt++; this_phy->an.status = STATUS_AN_COMPLETE; + this_phy->an.lp_bp_adv_ability = + (uint64_t)HAL_get_32bit_reg(this_phy->an_base_addr, + C10GB_AN_MR_LP_BASE_PG_CAPABILITY_1) | + ((uint64_t)HAL_get_32bit_reg(this_phy->an_base_addr, + C10GB_AN_MR_LP_BASE_PG_CAPABILITY_2) + << 16) | + ((uint64_t)HAL_get_32bit_reg(this_phy->an_base_addr, + C10GB_AN_MR_LP_BASE_PG_CAPABILITY_3) + << 32); /* Set data path to LT block, enable LT and timers */ HAL_set_32bit_reg_field(this_phy->lt_base_addr, @@ -204,57 +240,70 @@ PHY10GKR_autonegotiate_sm C10GB_TX_CTRL_PMA_DATA, TX_CTRL_LT); + /* Have both the local device and link partner advertised FEC ability? */ + if ((this_phy->fec_configured) && + (this_phy->an.lp_bp_adv_ability & (uint64_t)1U << (uint64_t)MR_ADV_FEC_ABILITY)) + { + /* Has either device requested FEC? */ + if ((this_phy->an.adv_ability & (uint64_t)1U + << (uint64_t)MR_ADV_FEC_REQUESTED) || + (this_phy->an.lp_bp_adv_ability & (uint64_t)1U + << (uint64_t)MR_ADV_FEC_REQUESTED)) + { + this_phy->fec_negotiated = C10GBKR_FEC_NEGOTIATED; + } + } + this_phy->lt.timer.start = PHY10GKR_get_current_time_ms(); } - break; + break; default: HAL_ASSERT(0); - break; + break; } } -/***************************************************************************//** - Please see phy.h for description +/** + * This private function enables the link training state machine, this enables the + * link training registers and then runs the link training algorithm. + * + * The connected transceiver must have a data rate of 10 Gbps and locked to a + * link partner with the same data rate for successful link training. */ void -PHY10GKR_link_training_sm -( - phy10gkr_instance_t * this_phy -) +phy_10gbasekr_lt(phy10gkr_instance_t *this_phy) { uint32_t c10gbkr_status = 0; - this_phy->lt.state = HAL_get_32bit_reg_field(this_phy->lt_base_addr, - C10GB_LT_TRAINING_SM); + this_phy->lt.state = HAL_get_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_TRAINING_SM); - switch(this_phy->lt.api_state) + switch (this_phy->lt.api_state) { case LT_API_SM_INIT: - if(C10GBKR_LT_PRESET == this_phy->lt.rx_request) + if (C10GBKR_LT_PRESET == this_phy->rx_calibration_request) { - HAL_set_32bit_reg(this_phy->lt_base_addr, C10GB_LT_CTRL, - (C10GB_LT_RESTART_EN_MASK | C10GB_LT_PRESET_MASK)); + HAL_set_32bit_reg(this_phy->lt_base_addr, + C10GB_LT_CTRL, + (C10GB_LT_RESTART_EN_MASK | C10GB_LT_PRESET_MASK)); } - else if(C10GBKR_LT_INITALISE == this_phy->lt.rx_request) + else if (C10GBKR_LT_INITALISE == this_phy->rx_calibration_request) { HAL_set_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_CTRL, - (C10GB_LT_RESTART_EN_MASK | C10GB_LT_INIT_MASK)); + C10GB_LT_CTRL, + (C10GB_LT_RESTART_EN_MASK | C10GB_LT_INIT_MASK)); } this_phy->lt.api_state = LT_API_SM_STATUS_UPDATE; - break; + break; case LT_API_SM_STATUS_UPDATE: - c10gbkr_status = HAL_get_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_STATUS); + c10gbkr_status = HAL_get_32bit_reg(this_phy->lt_base_addr, C10GB_LT_STATUS); - this_phy->lt.timer.end = PHY10GKR_get_current_time_ms() - - this_phy->lt.timer.start; + this_phy->lt.timer.end = PHY10GKR_get_current_time_ms() - this_phy->lt.timer.start; - if((c10gbkr_status & C10GB_LT_TRAINING_FAIL_MASK) || - this_phy->lt.timer.end > LT_SOFTWARE_WAIT_TIMER_MS) + if ((c10gbkr_status & C10GB_LT_TRAINING_FAIL_MASK) || + this_phy->lt.timer.end > LT_SOFTWARE_WAIT_TIMER_MS) { this_phy->lt.fail_cnt++; this_phy->lt.status = STATUS_LT_FAILURE; @@ -262,61 +311,83 @@ PHY10GKR_link_training_sm /* disable lt hardware in the case that the software timer * trigger the failure */ - HAL_set_32bit_reg_field(this_phy->lt_base_addr, - C10GB_LT_RESTART_EN, - 0x0); + HAL_set_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_RESTART_EN, 0x0); break; } - if(c10gbkr_status & C10GB_LT_REQ_TX_EQUAL_MASK) + if (c10gbkr_status & C10GB_LT_REQ_TX_EQUAL_MASK) { uint32_t tx_main_tap; uint32_t tx_post_tap; uint32_t tx_pre_tap; + uint32_t rcvd_coeff; + this_phy->lt.tx_equ_cnt++; - tx_main_tap = HAL_get_32bit_reg_field(this_phy->lt_base_addr, - C10GB_LT_TX_NEW_MAIN_TAP); - tx_post_tap = HAL_get_32bit_reg_field(this_phy->lt_base_addr, - C10GB_LT_TX_NEW_POST_TAP) - - C10GBKR_LT_POST_TAP_MAX_LIMIT; - tx_pre_tap = HAL_get_32bit_reg_field(this_phy->lt_base_addr, - C10GB_LT_TX_NEW_PRE_TAP) - - C10GBKR_LT_PRE_TAP_MAX_LIMIT; + rcvd_coeff = + HAL_get_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_NEW_RCVD_COEFF); + + if (rcvd_coeff & (COEFF_UPDATE_INITIALIZE | COEFF_UPDATE_PRESET)) + { + if (rcvd_coeff & COEFF_UPDATE_PRESET) + { + tx_main_tap = this_phy->main_preset_tap_coeff; + tx_post_tap = + this_phy->post_preset_tap_coeff - this_phy->post_max_tap_ceoff; + tx_pre_tap = this_phy->pre_preset_tap_coeff - this_phy->pre_max_tap_ceoff; + } + else + { + tx_main_tap = this_phy->main_initialize_tap_coeff; + tx_post_tap = + this_phy->post_initialize_tap_coeff - this_phy->post_max_tap_ceoff; + tx_pre_tap = + this_phy->pre_initialize_tap_coeff - this_phy->pre_max_tap_ceoff; + } + } + else + { + tx_main_tap = + HAL_get_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_TX_NEW_MAIN_TAP); + tx_post_tap = + HAL_get_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_TX_NEW_POST_TAP) - + this_phy->post_max_tap_ceoff; + tx_pre_tap = + HAL_get_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_TX_NEW_PRE_TAP) - + this_phy->pre_max_tap_ceoff; + } - PHY10GKR_serdes_tx_equalization(tx_main_tap, - tx_post_tap, - tx_pre_tap); + this_phy->xcvr_api.tx_equalization(this_phy->xcvr, + tx_main_tap, + tx_post_tap, + tx_pre_tap); /* signal to hardware to set tx status report field */ - HAL_set_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_TX_EQUAL, - C10GB_LT_TX_EQUAL_PRE_DONE_MASK | - C10GB_LT_TX_EQUAL_POST_DONE_MASK | - C10GB_LT_TX_EQUAL_MAIN_DONE_MASK | - C10GB_LT_TX_EQUAL_DONE_MASK); + HAL_set_32bit_reg( + this_phy->lt_base_addr, + C10GB_LT_TX_EQUAL, + C10GB_LT_TX_EQUAL_PRE_DONE_MASK | C10GB_LT_TX_EQUAL_POST_DONE_MASK | + C10GB_LT_TX_EQUAL_MAIN_DONE_MASK | C10GB_LT_TX_EQUAL_DONE_MASK); } - if((c10gbkr_status & C10GB_LT_REQ_RX_CAL_MASK) && - LOCAL_RXCVR_UNLOCKED == this_phy->lt.local_rxcvr) + if ((c10gbkr_status & C10GB_LT_REQ_RX_CAL_MASK) && + LOCAL_RXCVR_UNLOCKED == this_phy->lt.local_rxcvr) { /* signal to hardware to set tx coefficient update field */ - HAL_set_32bit_reg_field(this_phy->lt_base_addr, - C10GB_LT_RX_CAL_DONE, - 1U); + HAL_set_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_RX_CAL_DONE, 1U); - HAL_set_32bit_reg_field(this_phy->lt_base_addr, - C10GB_LT_RX_CAL_DONE, - 0U); + HAL_set_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_RX_CAL_DONE, 0U); this_phy->lt.rx_cal_cnt++; - if(C10GBKR_LT_PRESET == this_phy->lt.tx_request) + if (C10GBKR_LT_PRESET == this_phy->rx_calibration_request) { link_partner_calibration_sm(this_phy); } - else if(C10GBKR_LT_INITALISE == this_phy->lt.tx_request) + else if (C10GBKR_LT_INITALISE == this_phy->rx_calibration_request) { + /* check status report */ + this_phy->lt.local_rxcvr = LOCAL_RXCVR_LOCKED; this_phy->lt.rcvr_cnt++; @@ -325,14 +396,13 @@ PHY10GKR_link_training_sm C10GB_LT_LOCAL_RCVR_LOCKED, LOCAL_RXCVR_LOCKED); } - } - if(c10gbkr_status & C10GB_LT_SIGNAL_DETECT_MASK) + if (c10gbkr_status & C10GB_LT_SIGNAL_DETECT_MASK) { this_phy->lt.complete_cnt++; - /* Tx control: CL49 Data, PCS data transmitted to Serdes */ + /* Tx control: CL49 Data, PCS data */ HAL_set_32bit_reg_field(this_phy->tx_ctrl_base_addr, C10GB_TX_CTRL_PMA_DATA, TX_CTRL_DATA); @@ -340,79 +410,226 @@ PHY10GKR_link_training_sm this_phy->lt.status = STATUS_LT_COMPLETE; break; } - break; + break; default: HAL_ASSERT(0); - break; + break; } this_phy->lt.sm_cycle_cnt++; } -/***************************************************************************//** - Please see phy.h for description +/*------------------------Public Function-------------------------------------*/ +/** + * Please see core10gbasekr_phy.h for description + */ +void +PHY10GKR_cfg_struct_def_init(phy10gkr_cfg_t *cfg) +{ + phy10gkr_xcvr_api_t xcvr_api = {NULL}; + + cfg->fec_request = C10GBKR_DISABLE_FEC_REQUEST; + cfg->rx_calibration_request = C10GBKR_LT_PRESET; + + cfg->xcvr_api = xcvr_api; + + cfg->main_max_tap_ceoff = C10GBKR_LT_MAIN_TAP_MAX_LIMIT; + cfg->main_min_tap_ceoff = C10GBKR_LT_MAIN_TAP_MIN_LIMIT; + cfg->post_max_tap_ceoff = C10GBKR_LT_POST_TAP_MAX_LIMIT; + cfg->post_min_tap_ceoff = C10GBKR_LT_POST_TAP_MIN_LIMIT; + cfg->pre_max_tap_ceoff = C10GBKR_LT_PRE_TAP_MAX_LIMIT; + cfg->pre_min_tap_ceoff = C10GBKR_LT_PRE_TAP_MIN_LIMIT; + + cfg->main_preset_tap_coeff = C10GBKR_LT_PRESET_MAIN_TAP; + cfg->post_preset_tap_coeff = C10GBKR_LT_PRESET_POST_TAP; + cfg->pre_preset_tap_coeff = C10GBKR_LT_PRESET_PRE_TAP; + + cfg->main_initialize_tap_coeff = C10GBKR_LT_INITIALIZE_MAIN_TAP; + cfg->post_initialize_tap_coeff = C10GBKR_LT_INITIALIZE_POST_TAP; + cfg->pre_initialize_tap_coeff = C10GBKR_LT_INITIALIZE_PRE_TAP; +} + +/** + * Please see core10gbasekr_phy.h for description + */ +uint32_t +PHY10GKR_init(phy10gkr_instance_t *this_phy, addr_t base_addr, phy10gkr_cfg_t *cfg, void *xcvr) +{ + /* Set Core10GBaseKR PHY Base addresses */ + this_phy->base_addr = base_addr; + this_phy->an_base_addr = this_phy->base_addr | C10GB_AN_BASE_OFFSET; + this_phy->lt_base_addr = this_phy->base_addr | C10GB_LT_BASE_OFFSET; + this_phy->tx_ctrl_base_addr = this_phy->base_addr | C10GB_TX_CTRL_BASE_OFFSET; + this_phy->rx_status_base_addr = this_phy->base_addr | C10GB_RX_STATUS_BASE_OFFSET; + + /* User config error handling */ + if ((NULL == cfg)) + { + HAL_ASSERT(0); + return PHY10GKR_ERR_USER_CONFIG; /* Release build error */ + } + + if (NULL == xcvr) + { + HAL_ASSERT(0); + return PHY10GKR_ERR_NO_XCVR; /* Release build error */ + } + + /* setting configurations */ + this_phy->xcvr = xcvr; + this_phy->xcvr_api = cfg->xcvr_api; + + if (this_phy->xcvr_api.init == NULL || this_phy->xcvr_api.auto_neg_data_rate == NULL || + this_phy->xcvr_api.link_training_data_rate == NULL || this_phy->xcvr_api.cdr_lock == NULL || + this_phy->xcvr_api.ctle_cal == NULL || this_phy->xcvr_api.ctle_cal_status == NULL || + this_phy->xcvr_api.dfe_cal == NULL || this_phy->xcvr_api.dfe_cal_status == NULL || + this_phy->xcvr_api.reset_pcs_rx == NULL || this_phy->xcvr_api.tx_equalization == NULL) + { + /* function pointer assignment error */ + HAL_ASSERT(0); + return PHY10GKR_ERR_XCVR_API_FUNCTION_POINTER; /* Release build error */ + } + + /* Check if FEC configured in the IP, advertise ability if it exists */ + if (HAL_get_32bit_reg_field(this_phy->tx_ctrl_base_addr, C10GB_FEC_USE_CFG) != 0) + { + this_phy->fec_configured = C10GBKR_FEC_ABILITY; + } + else + { + this_phy->fec_configured = C10GBKR_NO_FEC_ABILITY; + } + + this_phy->fec_request = cfg->fec_request; + this_phy->rx_calibration_request = cfg->rx_calibration_request; + + this_phy->main_max_tap_ceoff = cfg->main_max_tap_ceoff; + this_phy->main_min_tap_ceoff = cfg->main_min_tap_ceoff; + this_phy->post_max_tap_ceoff = cfg->post_max_tap_ceoff; + this_phy->post_min_tap_ceoff = cfg->post_min_tap_ceoff; + this_phy->pre_max_tap_ceoff = cfg->pre_max_tap_ceoff; + this_phy->pre_min_tap_ceoff = cfg->pre_min_tap_ceoff; + + this_phy->main_preset_tap_coeff = cfg->main_preset_tap_coeff; + this_phy->post_preset_tap_coeff = cfg->post_preset_tap_coeff; + this_phy->pre_preset_tap_coeff = cfg->pre_preset_tap_coeff; + + this_phy->main_initialize_tap_coeff = cfg->main_initialize_tap_coeff; + this_phy->post_initialize_tap_coeff = cfg->post_initialize_tap_coeff; + this_phy->pre_initialize_tap_coeff = cfg->pre_initialize_tap_coeff; + + phy_10gbasekr_reset(this_phy); + + this_phy->xcvr_api.init(this_phy->xcvr); + + return 0; +} + +/** + * Please see core10gbasekr_phy.h for description */ uint32_t -PHY10GKR_10gbasekr_sm -( - phy10gkr_instance_t * this_phy -) +PHY10GKR_10gbasekr_sm(phy10gkr_instance_t *this_phy) { - switch(this_phy->c10gbkr_state) + if (this_phy == NULL) + { + HAL_ASSERT(0); + } + + switch (this_phy->c10gbkr_state) { case AN_SERDES_CONFIG: this_phy->c10gbkr_status = AN_SERDES_CONFIGURATION; - PHY10GKR_config(this_phy); - PHY10GKR_serdes_an_config(); + phy_10gbasekr_reset(this_phy); + HAL_set_32bit_reg_field(this_phy->tx_ctrl_base_addr, + C10GB_TX_CTRL_XCVR_LOS, + LANE_LOS_LOCK_TO_REF); + this_phy->xcvr_api.auto_neg_data_rate(this_phy->xcvr); this_phy->c10gbkr_state = AN_SM; - break; + break; case AN_SM: this_phy->c10gbkr_status = AN_IN_PROGRESS; - PHY10GKR_autonegotiate_sm(this_phy); - if(STATUS_AN_COMPLETE == this_phy->an.status) + phy_10gbasekr_an(this_phy); + if (STATUS_AN_COMPLETE == this_phy->an.status) { this_phy->c10gbkr_status = AN_COMPLETE; this_phy->c10gbkr_state = LT_SERDES_CONFIG; } - break; + break; case LT_SERDES_CONFIG: this_phy->c10gbkr_status = LT_SERDES_CONFIGURATION; - if(PHY10GKR_serdes_lt_config() >= 1) + HAL_set_32bit_reg_field(this_phy->tx_ctrl_base_addr, + C10GB_TX_CTRL_XCVR_LOS, + LANE_LOS_LOCK_TO_DATA); + this_phy->xcvr_api.link_training_data_rate(this_phy->xcvr); + + while (this_phy->xcvr_api.cdr_lock(this_phy->xcvr) != 0) { - this_phy->c10gbkr_status = LT_SERDES_CAL_FAILURE; - this_phy->c10gbkr_state = AN_SERDES_CONFIG; + this_phy->lt.timer.end = PHY10GKR_get_current_time_ms() - this_phy->lt.timer.start; + + /* determine if hardware or software timed out */ + if (this_phy->lt.timer.end >= LT_SOFTWARE_WAIT_TIMER_MS || + HAL_get_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_TRAINING_FAIL) == 1) + { + this_phy->c10gbkr_status = LT_SERDES_CAL_FAILURE; + break; + } } - else + + if (this_phy->c10gbkr_status != LT_SERDES_CAL_FAILURE) + { + this_phy->xcvr_api.ctle_cal(this_phy->xcvr); + + while (this_phy->xcvr_api.ctle_cal_status(this_phy->xcvr) != 0) + { + this_phy->lt.timer.end = + PHY10GKR_get_current_time_ms() - this_phy->lt.timer.start; + if (this_phy->lt.timer.end >= LT_SOFTWARE_WAIT_TIMER_MS || + HAL_get_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_TRAINING_FAIL) == + 1) + { + this_phy->c10gbkr_status = LT_SERDES_CAL_FAILURE; + break; + } + } + } + + if (this_phy->c10gbkr_status != LT_SERDES_CAL_FAILURE) { this_phy->c10gbkr_status = LT_SERDES_CAL_COMPLETE; this_phy->c10gbkr_state = LT_SM; } - break; + else + { + this_phy->c10gbkr_state = AN_SERDES_CONFIG; + } + + break; case LT_SM: this_phy->c10gbkr_status = LT_IN_PROGRESS; - PHY10GKR_link_training_sm(this_phy); + phy_10gbasekr_lt(this_phy); - if(STATUS_LT_FAILURE == this_phy->lt.status) + if (STATUS_LT_FAILURE == this_phy->lt.status) { /* reset the state machine for next time its called */ this_phy->c10gbkr_state = AN_SERDES_CONFIG; this_phy->c10gbkr_status = LT_FAILURE; } - else if(STATUS_LT_COMPLETE == this_phy->lt.status) + else if (STATUS_LT_COMPLETE == this_phy->lt.status) { this_phy->c10gbkr_state = LINK_ESTABLISHED_CHECK; this_phy->c10gbkr_status = LINK_ESTABLISHED; } - break; + break; case LINK_ESTABLISHED_CHECK: - if(PHY10GKR_serdes_cdr_lock() > 0) + if (this_phy->xcvr_api.cdr_lock(this_phy->xcvr) != 0) { /* reset the state machine for next time its called */ this_phy->c10gbkr_state = AN_SERDES_CONFIG; @@ -423,25 +640,38 @@ PHY10GKR_10gbasekr_sm { this_phy->c10gbkr_status = LINK_ESTABLISHED; } - break; + break; default: HAL_ASSERT(0); - break; + break; } return this_phy->c10gbkr_status; } -/***************************************************************************//** - Please see phy.h for description - */ -void -PHY10GKR_set_lane_los_signal -( - phy10gkr_instance_t * this_phy, - uint32_t state -) +uint8_t +PHY10GKR_get_ip_version(phy10gkr_instance_t *this_phy, + uint32_t *major, + uint32_t *minor, + uint32_t *sub) +{ + if (this_phy == NULL) + { + HAL_ASSERT(0); + return 1; /* release build error */ + } + + *major = HAL_get_32bit_reg_field(this_phy->tx_ctrl_base_addr, C10GB_IP_VERSION_MAJOR); + *minor = HAL_get_32bit_reg_field(this_phy->tx_ctrl_base_addr, C10GB_IP_VERSION_MINOR); + *sub = HAL_get_32bit_reg_field(this_phy->tx_ctrl_base_addr, C10GB_IP_VERSION_SUB); + return 0; +} + +uint8_t +PHY10GKR_get_driver_version(uint32_t *major, uint32_t *minor, uint32_t *patch) { - HAL_set_32bit_reg_field(this_phy->tx_ctrl_base_addr, - C10GB_TX_CTRL_XCVR_LOS, state); + *major = C10GBKR_VERSION_MAJOR; + *minor = C10GBKR_VERSION_MINOR; + *patch = C10GBKR_VERSION_PATCH; + return 0; } diff --git a/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy.h b/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy.h new file mode 100644 index 0000000..8bde4bb --- /dev/null +++ b/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy.h @@ -0,0 +1,515 @@ +/** + * Copyright 2022 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * @file core10gbasekr_phy.h + * @author Microchip FPGA Embedded Systems Solutions + * @brief Core10GBaseKR_PHY prototypes + * + */ + +/** + * @mainpage Core10GBaseKR_PHY Bare Metal Driver + * + * ============================================================================== + * Introduction + * ============================================================================== + * Core10GBaseKR_PHY is designed for the IEEE® 802.3-2012 specification and + * supports the Core10GBaseKR_PHY interface for Backplane operations. This + * configurable core provides the Physical (PHY) layer when used with a + * transceiver interface. This IP interfaces with the Ten Gigabit Media + * Independent Interface (XGMII) compliant Media Access Control (MAC) at the + * system side and the transceiver block at the line side. The physical layer is + * designed to work seamlessly with the PolarFire® and PolarFire SoC transceiver + * using the Physical Medium Attachment (PMA) mode. This user guide documents the + * features provided by the Core10GBaseKR_PHY embedded software driver. + * + * ============================================================================== + * Hardware Flow Dependencies + * ============================================================================== + * This driver covers the configuration details of features such as the clauses 72 + * (Link Training), 73 (Auto-negotiation), and 74 (Forward Error Correction) of + * IEEE802.3. + * + * See the [Core10GBaseKR_PHY User + * Guide](https://mi-v-ecosystem.github.io/redirects/miv-rv32-ip-user-guide-core10gbasekr_phy) for a + * detailed description of design requirements when interfacing the Core10GBaseKR_PHY to a + * transceiver. + * + * ============================================================================== + * Theory of Operation + * ============================================================================== + * The Core10GBaseKR_PHY driver functions are grouped into the following + * categories: + * - Configuration + * - Initialization + * - 10GBASE-KR + * - Clause74: Forward Error Correction (FEC) + * - Clause73: Auto-negotiation + * - Clause72: Link training + * + * -------------------------------- + * Configuration + * -------------------------------- + * The Core10GBaseKR_PHY driver requires an instance of a PHY configuration + * phy10gkr_cfg_t to be initialised. To load phy10gkr_cfg_t with default + * configurations, this configuration instance is passed by reference to + * PHY10GKR_cfg_struct_def_init(). This configuration structure may be overridden + * with alternative configurations before initialising the driver. + * + * The application must point to an instance of the Transceiver (XCVR) per instance + * of a phy10gkr_instance_t. The phy10gkr_instance_t structure members xcvr and + * xcvr_api must point to the XCVR that the Core10GBaseKR_PHY IP is interfacing with + * and the appropriate XCVR APIs for dynamic configuration. + * + * -------------------------------- + * Initialization + * -------------------------------- + * The Core10GBaseKR_PHY driver is initialized through a call to PHY10GKR_init(). + * The PHY10GKR_init() function must be called before calling any other + * Core10GBaseKR_PHY driver functions. + * + * -------------------------------- + * 10GBASE-KR + * -------------------------------- + * The full 10GBASE-KR flow is handled by calling PHY10GKR_10gbasekr_sm(). As + * this function is dependent on interacting with a transceiver, transceiver + * function pointers must be configured by the user to point to the transceiver + * APIs that dynamically configure the transceiver implemented in the hardware + * design. + * + * Each time PHY10GKR_10gbasekr_sm() is in the AN_SERDES_CONFIG state, the + * private function phy_10gbasekr_reset(), is called, which will load any user + * configurations to the Core registers and resets all algorithm and debug counters. + * + * This API uses two private function calls, phy_10gbasekr_an() and phy_10gbasekr_lt(), + * to enable and interact with clause 72 and 73 hardware blocks within the + * Core10GBaseKR_PHY IP. + * + * -------------------------------- + * Clause74: FEC + * -------------------------------- + * To enable FEC, FEC must be configured in the Core10GBaseKR_PHY IP. See the + * [Core10GBaseKR_PHY User + * Guide](https://mi-v-ecosystem.github.io/redirects/miv-rv32-ip-user-guide-core10gbasekr_phy) for a + * detailed description of how to enable FEC logic using the IP configurator. + * + * During auto-negotiation initialization, if the FEC block has been configured + * in the Core, the driver will set the FEC ability bit 46 in the advertisement + * ability DME page. + * + * The fec_request member within the phy10gkr_cfg_t structure may be set prior + * to driver initialisation to indicate that the driver should set the + * FEC request bit 47 in the advertisement ability clause 73 DME page. The driver + * implements error checking which identifies if fec_request is set when FEC is + * not configured within the Core. + * + * -------------------------------- + * Clause73: Auto-negotiation + * -------------------------------- + * The IEEE802.3 clause 73 auto-negotiation is enabled and executed by the private + * function, phy_10gbasekr_an(). PHY10GKR_10gbasekr() uses this private function + * enable auto-negotiation and determines when the hardware has reached the + * AN_GOOD_CHECK state. + * + * -------------------------------- + * Clause72: Link Training + * -------------------------------- + * The IEEE802.3 clause 72 link training is enabled and executed by the private + * function phy_10gbasekr_lt(). The Core10GBaseKR_PHY IP and the + * Core10GBaseKR_PHY embedded software driver together carry out the link + * training. The driver initiates the link training and takes appropriate actions + * depending on the events indicated by the 10GBaseKR status register bits during + * the link training process. + * + * Training Failure: The training failure bit is set by the IP when the + * Core10GBaseKR_PHY link training timer exceeds 500 ms. The driver also + * implements a soft timer as an additional protection layer. PHY10GKR_get_current_time_ms() + * must be overridden by instantiating this function in user code, so that the + * current time of a timer will be returned in milli-seconds. When this status + * is set by Core10GBaseKR_PHY, the embedded software must reduce the XCVR data rate + * by calling PHY10GKR_serdes_an_config() and restart the auto-negotiation state + * machine by calling phy_10gbasekr_an(). + * + * Rx Calibration: The IP sets this status bit to indicate that there is a + * received status report of Max/Min/Updated that the Rx calibration algorithm + * must handle. The maximum to minimum sweep algorithm described in the + * [Core10GBaseKR_PHY User + * Guide](https://mi-v-ecosystem.github.io/redirects/miv-rv32-ip-user-guide-core10gbasekr_phy) is + * implemented by the functions which are defined within core10gbasekr_phy_link_training.h. + * + * After the Rx calibration algorithm completes, the driver updates the + * transmit coefficient with new transmitter tap, which is sent to the + * link partner. + * + * Tx Equalization: This status bit indicates that the received coefficient + * update has been updated and that the firmware needs to update the transceiver + * transmitter taps. The driver hands off the new coefficient settings to the + * transceiver using the PHY10GKR_serdes_tx_equalization() weak function, + * which must be overridden. + * + * Signal Detect: When the driver identifies that this bit has been set by the + * Core10GBaseKR_PHY IP, it sets the link training complete flag. The IP updates + * this status bit when both the transmitted and received status reports have the + * receiver ready bit set. This indicates that both devices have completed their + * Rx calibration algorithm. + */ +#ifndef CORE10GBASEKR_PHY_H_ +#define CORE10GBASEKR_PHY_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "core10gbasekr_phy_types.h" +#include "core10gbasekr_phy_reg.h" + +/** + * Hardware and software timer timeouts. + */ +#define MAX_WAIT_TIMER_500MS (161000000U) +#define LT_SOFTWARE_WAIT_TIMER_MS (500U) + +/** + * CORE10GBASEKR_PHY VERSION TAGS + * ============================ + * The version tags define the major, minor and patch driver release tags + */ +#define C10GBKR_VERSION_MAJOR (3U) +#define C10GBKR_VERSION_MINOR (0U) +#define C10GBKR_VERSION_PATCH (107U) + +/** + * CORE10GBASEKR_PHY FEC ABILITY + * ============================ + * This defines that the auto-negotiation advertisement FEC ability bit should be set + * as the IP is configured with FEC logic. + */ +#define C10GBKR_FEC_ABILITY (1U) + +/** + * CORE10GBASEKR_PHY NO FEC ABILITY + * ============================ + * This defines that the auto-negotiation advertisement FEC ability bit should be + * cleared as the IP is not configured with FEC logic. + */ +#define C10GBKR_NO_FEC_ABILITY (0U) + +/** + * CORE10GBASEKR_PHY ENABLE FEC REQUEST + * ============================ + * This defines that the auto-negotiation advertisement FEC request bit should be set + * if the IP is configured with the FEC logic. + */ +#define C10GBKR_ENABLE_FEC_REQUEST (1U) + +/** + * CORE10GBASEKR_PHY DISABLE FEC REQUEST + * ============================ + * This defines that the auto-negotiation advertisement FEC request bit should be + * cleared if the IP is configured with the FEC logic. + */ +#define C10GBKR_DISABLE_FEC_REQUEST (0U) + +/** + * CORE10GBASEKR_PHY FEC NEGOTIATED + * ============================ + * This defines that FEC was negotiated during auto-negotiation + */ +#define C10GBKR_FEC_NEGOTIATED (1U) + +/** + * CORE10GBASEKR_PHY FEC NOT NEGOTIATED + * ============================ + * This defines that FEC was not negotiated during auto-negotiation + */ +#define C10GBKR_FEC_NOT_NEGOTIATED (0U) + +/** + * CORE10GBASEKR_PHY LT MAX/MIN LIMITS + * ============================ + * The max/min limit constants define the XCVR tap coefficient limits. These + * constants can be overridden based on the XCVR, which is integrated into a + * specific design. + * + * Note: Post and Pre tap maximum limits are absolute. + */ +#ifndef C10GBKR_LT_MAIN_TAP_MAX_LIMIT +#define C10GBKR_LT_MAIN_TAP_MAX_LIMIT (41U) +#endif + +#ifndef C10GBKR_LT_MAIN_TAP_MIN_LIMIT +#define C10GBKR_LT_MAIN_TAP_MIN_LIMIT (26U) +#endif + +#ifndef C10GBKR_LT_POST_TAP_MAX_LIMIT +#define C10GBKR_LT_POST_TAP_MAX_LIMIT (16U) +#endif + +#ifndef C10GBKR_LT_POST_TAP_MIN_LIMIT +#define C10GBKR_LT_POST_TAP_MIN_LIMIT (0U) +#endif + +#ifndef C10GBKR_LT_PRE_TAP_MAX_LIMIT +#define C10GBKR_LT_PRE_TAP_MAX_LIMIT (5U) +#endif + +#ifndef C10GBKR_LT_PRE_TAP_MIN_LIMIT +#define C10GBKR_LT_PRE_TAP_MIN_LIMIT (0U) +#endif + +/** + * CORE10GBASEKR_PHY PRESET + * ============================ + * The preset constants define the XCVR tap coefficient settings for a preset + * request. They can be overridden based on the XCVR, which is integrated into a + * specific design. + * + * Note: Post and Pre tap maximum limits are absolute. + */ +#ifndef C10GBKR_LT_PRESET_MAIN_TAP +#define C10GBKR_LT_PRESET_MAIN_TAP C10GBKR_LT_MAIN_TAP_MAX_LIMIT +#endif + +#ifndef C10GBKR_LT_PRESET_POST_TAP +#define C10GBKR_LT_PRESET_POST_TAP C10GBKR_LT_POST_TAP_MAX_LIMIT +#endif + +#ifndef C10GBKR_LT_PRESET_PRE_TAP +#define C10GBKR_LT_PRESET_PRE_TAP C10GBKR_LT_PRE_TAP_MAX_LIMIT +#endif + +/** + * CORE10GBASEKR_PHY INIT + * ============================ + * The initialize constants define the coefficient settings, which is set + * when an initialize request is received from the link partner. These constants + * should be updated if there is no desire to calibrate the links. + */ +#ifndef C10GBKR_LT_INITIALIZE_MAIN_TAP +#define C10GBKR_LT_INITIALIZE_MAIN_TAP C10GBKR_LT_MAIN_TAP_MIN_LIMIT +#endif + +#ifndef C10GBKR_LT_INITIALIZE_POST_TAP +#define C10GBKR_LT_INITIALIZE_POST_TAP C10GBKR_LT_POST_TAP_MIN_LIMIT +#endif + +#ifndef C10GBKR_LT_INITIALIZE_PRE_TAP +#define C10GBKR_LT_INITIALIZE_PRE_TAP C10GBKR_LT_PRE_TAP_MIN_LIMIT +#endif + +/** + * CORE10GBASEKR_PHY LP REQUEST + * ============================ + * This constant defines the request, which will be sent to the link partner and + * determines which algorithm will be implemented to calibrate the link partner. + */ +#ifndef C10GBKR_LT_INITIAL_REQUEST +#define C10GBKR_LT_INITIAL_REQUEST C10GBKR_LT_PRESET +#endif + +/** + * CORE10GBASEKR_PHY AN LINK FAIL INHIBIT TIMER + * ============================ + * This constant defines the auto-negotiation link fail inhibit timer timeout in + * milli-seconds. + */ +#ifndef C10GBKR_AN_LINK_FAIL_INHITBIT_TIMER +#define C10GBKR_AN_LINK_FAIL_INHITBIT_TIMER (500U) +#endif + +/*------------------------Public Function-------------------------------------*/ +/** + * PHY10GKR_cfg_struct_def_init() loads the PHY configuration struct + * as default. + * + * @param cfg + * The cfg parameter specifies the PHY configuration instance. + * + * @return + * This function does not return a value. + * + * @example + * @code + * #include "core10gbasekr_phy.h" + * int main(void) + * { + * PHY10GKR_cfg_struct_def_init(&phy_cfg); + * phy_cfg.fec_requested = 1; + * + * PHY10GKR_init(&xcvr, &g_phy, CORE10GBKR_0_PHY_BASE_ADDR); + * PHY10GKR_config(&g_phy, &phy_cfg); + * return (0u); + * } + * @endcode + */ +void PHY10GKR_cfg_struct_def_init(phy10gkr_cfg_t *cfg); + +/** + * PHY10GKR_init() initializes the Core10GBaseKR_PHY bare-metal driver. This + * function sets the base address of the Auto-negotiation, link-training, tx + * control, and rx status registers. + * + * @param this_phy + * The this_phy parameter specifies the PHY instance. + * + * @param base_addr + * The base_addr specifies the base address of the IP block. + * + * @param cfg + * The cfg parameter specifies the PHY configuration instance. + * + * @param xcvr + * This is a pointer to the instance of XCVR which is connected to this IP. + * + * @return + * This function returns success or failure, 0 implies success. On failure this + * function will return phy10gkr_error_t enumeration which indicates the error type. + * + * @example + * @code + * #include "core10gbasekr_phy.h" + * int main(void) + * { + * void * xcvr; + * xcvr.base_addr = 0xFFFFFFFF; + * xcvr.lane = 1; + * xcvr.serdes = 2; + * + * PHY10GKR_init(&g_phy, CORE10GBKR_0_PHY_BASE_ADDR, &phy_cfg ,&xcvr); + * return (0u); + * } + * @endcode + */ +uint32_t PHY10GKR_init(phy10gkr_instance_t *this_phy, + addr_t base_addr, + phy10gkr_cfg_t *cfg, + void *xcvr); + +/** + * PHY10GKR_10gbasekr_sm() executes the full 10GBASE-KR flow required to + * complete the auto-negotiation and link training. + * + * The 10GBASE-KR status enumeration allows the user to debug the auto-negotiation + * and link training algorithms. + * + * @param this_phy + * The this_phy parameter specifies the PHY instance. + * + * @return + * This function returns the phy10gkr_status_t enumeration which indicates the status + * of the API state machine. 0 implies that a link has been established. + * + * @example + * @code + * #include "core10gbasekr_phy.h" + * int main(void) + * { + * uint32_t status; + * PHY10GKR_cfg_struct_def_init(&phy_cfg); + * phy_cfg.fec_requested = 1; + * PHY10GKR_init(&g_phy, CORE10GBKR_0_PHY_BASE_ADDR, &phy_cfg, &xcvr); + * while(1) + * { + * status = PHY10GKR_10gbasekr_sm(&g_phy); + * if(LINK_ESTABLISHED == status) + * { + * break; + * } + * } + * return (0u); + * } + * @endcode + */ +uint32_t PHY10GKR_10gbasekr_sm(phy10gkr_instance_t *this_phy); + +/** + * PHY10GKR_get_current_time_ms() is a weak function that can be overridden + * by the user to get the current time in milli-seconds. + * + * @return + * This function returns the time in milli-seconds. + */ +uint32_t __attribute__((weak)) PHY10GKR_get_current_time_ms(void); + +/** + * PHY10GKR_get_ip_version() retrieves the IP version tags, the tags are passed by + * reference as parameters and updated by this function. This function must be + * called after initialization as there is a dependency on the instance of a + * Core10GBaseKR_PHY instance. + * + * @param this_phy + * The this_phy parameter specifies the PHY instance. + * + * @param major + * This parameter identifies the major version number. + * + * @param minor + * This parameter identifies the minor version number. + * + * @param sub + * This parameter identifies the sub version number. + * + * @return + * This function returns 0 on success. + * + * @example + * @code + * #include "core10gbasekr_phy.h" + * int main(void) + * { + * uint32_t major, + * uint32_t minor, + * uint32_t sub, + * + * PHY10GKR_cfg_struct_def_init(&phy_cfg); + * PHY10GKR_init(&g_phy, CORE10GBKR_0_PHY_BASE_ADDR, &phy_cfg, &xcvr); + * + * PHY10GKR_get_ip_version(&g_phy, &major, &minor, &sub); + * return (0u); + * } + * @endcode + */ +uint8_t PHY10GKR_get_ip_version(phy10gkr_instance_t *this_phy, + uint32_t *major, + uint32_t *minor, + uint32_t *sub); + +/** + * PHY10GKR_get_driver_version() retrieves the driver version tags, the tags are + * passed by reference as parameters and updated by this function. + * + * @param major + * This parameter identifies the major version number. + * + * @param minor + * This parameter identifies the minor version number. + * + * @param patch + * This parameter identifies the patch version number. + * + * @return + * This function returns 0 on success. + * + * @example + * @code + * #include "core10gbasekr_phy.h" + * int main(void) + * { + * uint32_t major, + * uint32_t minor, + * uint32_t patch, + + * PHY10GKR_get_driver_version(&major, &minor, &patch); + * return (0u); + * } + * @endcode + */ +uint8_t PHY10GKR_get_driver_version(uint32_t *major, uint32_t *minor, uint32_t *patch); + +#ifdef __cplusplus +} +#endif + +#endif /* CORE10GBASEKR_PHY_H_ */ diff --git a/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_link_training.c b/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_link_training.c index e2225c1..f717407 100644 --- a/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_link_training.c +++ b/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_link_training.c @@ -1,83 +1,85 @@ -/***************************************************************************//** +/** * Copyright 2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * * @file core10gbasekr_phy_link_training.c * @author Microchip FPGA Embedded Systems Solutions - * @brief PHY software configuration + * @brief Core10GBaseKR PHY link training prototypes * */ -#include "phy.h" + +#include "core10gbasekr_phy.h" #include "core10gbasekr_phy_link_training.h" /*------------------------Private Variables-----------------------------------*/ uint32_t prbs_arr[64] = {0}; uint32_t prbs_cnt = 0; -/***************************************************************************//** - Please see core10gbasekr_phy_link_training.h for description +/*------------------------Private Functions-----------------------------------*/ +/** + * This phy_10gbasekr_dfe_cal is private function which uses the XCVR APIs to set + * and check DFE calibration for a set timeout in milli-seconds + */ +static uint32_t +phy_10gbasekr_dfe_cal(phy10gkr_instance_t *this_phy, uint32_t timeout_ms) +{ + this_phy->xcvr_api.dfe_cal(this_phy->xcvr); + + uint32_t start_time = PHY10GKR_get_current_time_ms(); + uint32_t end_time = 0; + do + { + if (this_phy->xcvr_api.dfe_cal_status(this_phy->xcvr) == 0) + { + this_phy->xcvr_api.reset_pcs_rx(this_phy->xcvr); + return 0; + } + end_time = PHY10GKR_get_current_time_ms() - start_time; + } while (end_time < timeout_ms); + + this_phy->xcvr_api.reset_pcs_rx(this_phy->xcvr); + return 1; +} + +/** + * Please see core10gbasekr_phy_link_training.h for description */ void -link_partner_calibration_sm -( - phy10gkr_instance_t * this_phy -) +link_partner_calibration_sm(phy10gkr_instance_t *this_phy) { - switch(this_phy->lt.lp_cal_sweep_state) + switch (this_phy->lt.lp_cal_sweep_state) { case MAIN_TAP: link_partner_main_sweep(this_phy); - break; + break; case POST_TAP: link_partner_post_sweep(this_phy); - break; + break; case PRE_TAP: link_partner_pre_sweep(this_phy); - break; + break; default: HAL_ASSERT(0); - break; + break; } } -/***************************************************************************//** - Please see core10gbasekr_phy_link_training.h for description +/** + * Please see core10gbasekr_phy_link_training.h for description */ void -link_partner_main_sweep -( - phy10gkr_instance_t * this_phy -) +link_partner_main_sweep(phy10gkr_instance_t *this_phy) { - phy10gkr_coeff_status_report_t tap_coeff = HAL_get_32bit_reg_field( - this_phy->lt_base_addr, - C10GB_LT_RCVD_COEFF_MAIN_VALUE); + phy10gkr_coeff_status_report_t tap_coeff = + HAL_get_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_RCVD_COEFF_MAIN_VALUE); - if(this_phy->lt.main.lp_tap_cal_state == TAP_OPTIMISE_CAL) + if (this_phy->lt.main.lp_tap_cal_state == TAP_OPTIMISE_CAL) { - if(this_phy->lt.main.optimal_cnt == (this_phy->lt.main.optimal_index)) + if (this_phy->lt.main.optimal_cnt == (this_phy->lt.main.optimal_index)) { lt_tap_increment(this_phy, POST_TAP); this_phy->lt.post.cnt++; @@ -93,41 +95,39 @@ link_partner_main_sweep } else { - switch(tap_coeff) + switch (tap_coeff) { case LT_COEFF_STATUS_MAX: - prbs_arr[prbs_cnt] = HAL_get_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_PRBS_ERR_WRD); + prbs_arr[prbs_cnt] = + HAL_get_32bit_reg(this_phy->lt_base_addr, C10GB_LT_PRBS_ERR_WRD); prbs_cnt++; lt_tap_decrement(this_phy, MAIN_TAP); this_phy->lt.main.cnt++; this_phy->lt.main.dec_cnt++; - break; + break; case LT_COEFF_STATUS_NOT_UPDATED: lt_tap_hold(this_phy, MAIN_TAP); this_phy->lt.main.cnt++; - break; + break; case LT_COEFF_STATUS_UPDATED: - prbs_arr[prbs_cnt] = HAL_get_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_PRBS_ERR_WRD); + prbs_arr[prbs_cnt] = + HAL_get_32bit_reg(this_phy->lt_base_addr, C10GB_LT_PRBS_ERR_WRD); prbs_cnt++; lt_tap_decrement(this_phy, MAIN_TAP); this_phy->lt.main.cnt++; this_phy->lt.main.dec_cnt++; - break; + break; case LT_COEFF_STATUS_MIN: - prbs_arr[prbs_cnt] = HAL_get_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_PRBS_ERR_WRD); + prbs_arr[prbs_cnt] = + HAL_get_32bit_reg(this_phy->lt_base_addr, C10GB_LT_PRBS_ERR_WRD); prbs_cnt++; - this_phy->lt.main.optimal_index = lt_get_optimal_tap_index( - prbs_arr, - prbs_cnt); + this_phy->lt.main.optimal_index = lt_get_optimal_tap_index(prbs_arr, prbs_cnt); - if(this_phy->lt.main.optimal_index == 0) + if (this_phy->lt.main.optimal_index == 0) { lt_tap_increment(this_phy, POST_TAP); this_phy->lt.post.cnt++; @@ -141,31 +141,27 @@ link_partner_main_sweep lt_tap_increment(this_phy, MAIN_TAP); this_phy->lt.main.optimal_cnt++; } - break; + break; default: HAL_ASSERT(0); - break; + break; } } } -/***************************************************************************//** - Please see core10gbasekr_phy_link_training.h for description +/** + * Please see core10gbasekr_phy_link_training.h for description */ void -link_partner_post_sweep -( - phy10gkr_instance_t * this_phy -) +link_partner_post_sweep(phy10gkr_instance_t *this_phy) { - phy10gkr_coeff_status_report_t tap_coeff = HAL_get_32bit_reg_field( - this_phy->lt_base_addr, - C10GB_LT_RCVD_COEFF_POST_VALUE); + phy10gkr_coeff_status_report_t tap_coeff = + HAL_get_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_RCVD_COEFF_POST_VALUE); - if(this_phy->lt.post.lp_tap_cal_state == TAP_OPTIMISE_CAL) + if (this_phy->lt.post.lp_tap_cal_state == TAP_OPTIMISE_CAL) { - if(this_phy->lt.post.optimal_cnt == (this_phy->lt.post.optimal_index)) + if (this_phy->lt.post.optimal_cnt == (this_phy->lt.post.optimal_index)) { lt_tap_increment(this_phy, PRE_TAP); this_phy->lt.pre.cnt++; @@ -181,41 +177,39 @@ link_partner_post_sweep } else { - switch(tap_coeff) + switch (tap_coeff) { case LT_COEFF_STATUS_MAX: - prbs_arr[prbs_cnt] = HAL_get_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_PRBS_ERR_WRD); + prbs_arr[prbs_cnt] = + HAL_get_32bit_reg(this_phy->lt_base_addr, C10GB_LT_PRBS_ERR_WRD); prbs_cnt++; lt_tap_decrement(this_phy, POST_TAP); this_phy->lt.post.cnt++; this_phy->lt.post.dec_cnt++; - break; + break; case LT_COEFF_STATUS_NOT_UPDATED: lt_tap_hold(this_phy, POST_TAP); this_phy->lt.post.cnt++; - break; + break; case LT_COEFF_STATUS_UPDATED: - prbs_arr[prbs_cnt] = HAL_get_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_PRBS_ERR_WRD); + prbs_arr[prbs_cnt] = + HAL_get_32bit_reg(this_phy->lt_base_addr, C10GB_LT_PRBS_ERR_WRD); prbs_cnt++; lt_tap_decrement(this_phy, POST_TAP); this_phy->lt.post.cnt++; this_phy->lt.post.dec_cnt++; - break; + break; case LT_COEFF_STATUS_MIN: - prbs_arr[prbs_cnt] = HAL_get_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_PRBS_ERR_WRD); + prbs_arr[prbs_cnt] = + HAL_get_32bit_reg(this_phy->lt_base_addr, C10GB_LT_PRBS_ERR_WRD); prbs_cnt++; - this_phy->lt.post.optimal_index = lt_get_optimal_tap_index( - prbs_arr, - prbs_cnt); + this_phy->lt.post.optimal_index = lt_get_optimal_tap_index(prbs_arr, prbs_cnt); - if(this_phy->lt.post.optimal_index == 0) + if (this_phy->lt.post.optimal_index == 0) { lt_tap_increment(this_phy, PRE_TAP); this_phy->lt.pre.cnt++; @@ -229,52 +223,45 @@ link_partner_post_sweep lt_tap_increment(this_phy, POST_TAP); this_phy->lt.post.optimal_cnt++; } - break; + break; default: HAL_ASSERT(0); - break; + break; } } } -/***************************************************************************//** - link partner pre cursor sweep +/** + * Please see core10gbasekr_phy_link_training.h for description */ void -link_partner_pre_sweep -( - phy10gkr_instance_t * this_phy -) +link_partner_pre_sweep(phy10gkr_instance_t *this_phy) { - phy10gkr_coeff_status_report_t tap_coeff = HAL_get_32bit_reg_field( - this_phy->lt_base_addr, - C10GB_LT_RCVD_COEFF_PRE_VALUE); + phy10gkr_coeff_status_report_t tap_coeff = + HAL_get_32bit_reg_field(this_phy->lt_base_addr, C10GB_LT_RCVD_COEFF_PRE_VALUE); - if(this_phy->lt.pre.lp_tap_cal_state == TAP_OPTIMISE_CAL) + if (this_phy->lt.pre.lp_tap_cal_state == TAP_OPTIMISE_CAL) { - - if(this_phy->lt.pre.optimal_cnt == (this_phy->lt.pre.optimal_index)) + if (this_phy->lt.pre.optimal_cnt == (this_phy->lt.pre.optimal_index)) { - while((PHY10GKR_serdes_dfe_cal() == 1) && - (STATUS_LT_FAILURE != this_phy->lt.status)) + while ((phy_10gbasekr_dfe_cal(this_phy, 10) != 0) && + (STATUS_LT_FAILURE != this_phy->lt.status)) { - uint32_t c10gbkr_status = HAL_get_32bit_reg( - this_phy->lt_base_addr, - C10GB_LT_STATUS); + uint32_t c10gbkr_status = + HAL_get_32bit_reg(this_phy->lt_base_addr, C10GB_LT_STATUS); - this_phy->lt.timer.end = PHY10GKR_get_current_time_ms() - - this_phy->lt.timer.start; + this_phy->lt.timer.end = PHY10GKR_get_current_time_ms() - this_phy->lt.timer.start; - if((c10gbkr_status & C10GB_LT_TRAINING_FAIL_MASK) || - this_phy->lt.timer.end > LT_SOFTWARE_WAIT_TIMER_MS) + if ((c10gbkr_status & C10GB_LT_TRAINING_FAIL_MASK) || + this_phy->lt.timer.end > LT_SOFTWARE_WAIT_TIMER_MS) { this_phy->lt.status = STATUS_LT_FAILURE; break; } } - if(STATUS_LT_FAILURE != this_phy->lt.status) + if (STATUS_LT_FAILURE != this_phy->lt.status) { /* All sweeps complete set to best ber index */ this_phy->lt.local_rxcvr = LOCAL_RXCVR_LOCKED; @@ -295,62 +282,58 @@ link_partner_pre_sweep } else { - switch(tap_coeff) + switch (tap_coeff) { case LT_COEFF_STATUS_MAX: - prbs_arr[prbs_cnt] = HAL_get_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_PRBS_ERR_WRD); + prbs_arr[prbs_cnt] = + HAL_get_32bit_reg(this_phy->lt_base_addr, C10GB_LT_PRBS_ERR_WRD); prbs_cnt++; lt_tap_decrement(this_phy, PRE_TAP); this_phy->lt.pre.cnt++; this_phy->lt.pre.dec_cnt++; - break; + break; case LT_COEFF_STATUS_NOT_UPDATED: lt_tap_hold(this_phy, PRE_TAP); this_phy->lt.pre.cnt++; - break; + break; case LT_COEFF_STATUS_UPDATED: - prbs_arr[prbs_cnt] = HAL_get_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_PRBS_ERR_WRD); + prbs_arr[prbs_cnt] = + HAL_get_32bit_reg(this_phy->lt_base_addr, C10GB_LT_PRBS_ERR_WRD); prbs_cnt++; lt_tap_decrement(this_phy, PRE_TAP); this_phy->lt.pre.cnt++; this_phy->lt.pre.dec_cnt++; - break; + break; case LT_COEFF_STATUS_MIN: - prbs_arr[prbs_cnt] = HAL_get_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_PRBS_ERR_WRD); + prbs_arr[prbs_cnt] = + HAL_get_32bit_reg(this_phy->lt_base_addr, C10GB_LT_PRBS_ERR_WRD); prbs_cnt++; - this_phy->lt.pre.optimal_index = lt_get_optimal_tap_index( - prbs_arr, - prbs_cnt); + this_phy->lt.pre.optimal_index = lt_get_optimal_tap_index(prbs_arr, prbs_cnt); - if(this_phy->lt.post.optimal_index == 0) + if (this_phy->lt.post.optimal_index == 0) { - while((PHY10GKR_serdes_dfe_cal() == 1) && - (STATUS_LT_FAILURE != this_phy->lt.status)) + while ((phy_10gbasekr_dfe_cal(this_phy, 10) != 0) && + (STATUS_LT_FAILURE != this_phy->lt.status)) { - uint32_t c10gbkr_status = HAL_get_32bit_reg( - this_phy->lt_base_addr, - C10GB_LT_STATUS); + uint32_t c10gbkr_status = + HAL_get_32bit_reg(this_phy->lt_base_addr, C10GB_LT_STATUS); - this_phy->lt.timer.end = PHY10GKR_get_current_time_ms() - - this_phy->lt.timer.start; + this_phy->lt.timer.end = + PHY10GKR_get_current_time_ms() - this_phy->lt.timer.start; - if((c10gbkr_status & C10GB_LT_TRAINING_FAIL_MASK) - || (this_phy->lt.timer.end > - LT_SOFTWARE_WAIT_TIMER_MS)) + if ((c10gbkr_status & C10GB_LT_TRAINING_FAIL_MASK) || + (this_phy->lt.timer.end > LT_SOFTWARE_WAIT_TIMER_MS)) { this_phy->lt.status = STATUS_LT_FAILURE; break; } } - if(STATUS_LT_FAILURE != this_phy->lt.status) + if (STATUS_LT_FAILURE != this_phy->lt.status) { /* All sweeps complete set to best ber index */ this_phy->lt.local_rxcvr = LOCAL_RXCVR_LOCKED; @@ -369,148 +352,126 @@ link_partner_pre_sweep lt_tap_increment(this_phy, PRE_TAP); this_phy->lt.pre.optimal_cnt++; } - break; + break; default: HAL_ASSERT(0); - break; + break; } } } -/***************************************************************************//** - * set the decrement bit of a specific transmit equalizer tap register +/** + * Please see core10gbasekr_phy_link_training.h for description */ void -lt_tap_decrement -( - phy10gkr_instance_t * this_phy, - phy10gkr_tx_equalizer_tap_t tap_type -) +lt_tap_decrement(phy10gkr_instance_t *this_phy, phy10gkr_tx_equalizer_tap_t tap_type) { - switch(tap_type) + switch (tap_type) { case MAIN_TAP: HAL_set_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_TX_COEFF_CFG, - C10GB_LT_TX_DEC_MAIN_MASK); - break; + C10GB_LT_TX_COEFF_CFG, + C10GB_LT_TX_DEC_MAIN_MASK); + break; case POST_TAP: HAL_set_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_TX_COEFF_CFG, - C10GB_LT_TX_DEC_POST_MASK); - break; + C10GB_LT_TX_COEFF_CFG, + C10GB_LT_TX_DEC_POST_MASK); + break; case PRE_TAP: HAL_set_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_TX_COEFF_CFG, - C10GB_LT_TX_DEC_PRE_MASK); - break; + C10GB_LT_TX_COEFF_CFG, + C10GB_LT_TX_DEC_PRE_MASK); + break; default: HAL_ASSERT(0); - break; + break; } } - -/***************************************************************************//** - * set the hold bit of a specific transmit equalizer tap register +/** + * Please see core10gbasekr_phy_link_training.h for description */ void -lt_tap_hold -( - phy10gkr_instance_t * this_phy, - phy10gkr_tx_equalizer_tap_t tap_type -) +lt_tap_hold(phy10gkr_instance_t *this_phy, phy10gkr_tx_equalizer_tap_t tap_type) { - switch(tap_type) + switch (tap_type) { case MAIN_TAP: HAL_set_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_TX_COEFF_CFG, - C10GB_LT_TX_HOLD_MAIN_MASK); - break; + C10GB_LT_TX_COEFF_CFG, + C10GB_LT_TX_HOLD_MAIN_MASK); + break; case POST_TAP: HAL_set_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_TX_COEFF_CFG, - C10GB_LT_TX_HOLD_POST_MASK); - break; + C10GB_LT_TX_COEFF_CFG, + C10GB_LT_TX_HOLD_POST_MASK); + break; case PRE_TAP: HAL_set_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_TX_COEFF_CFG, - C10GB_LT_TX_HOLD_PRE_MASK); - break; + C10GB_LT_TX_COEFF_CFG, + C10GB_LT_TX_HOLD_PRE_MASK); + break; default: HAL_ASSERT(0); - break; + break; } } -/***************************************************************************//** - * set the increment bit of a specific transmit equalizer tap register +/** + * Please see core10gbasekr_phy_link_training.h for description */ void -lt_tap_increment -( - phy10gkr_instance_t * this_phy, - phy10gkr_tx_equalizer_tap_t tap_type -) +lt_tap_increment(phy10gkr_instance_t *this_phy, phy10gkr_tx_equalizer_tap_t tap_type) { - switch(tap_type) + switch (tap_type) { case MAIN_TAP: HAL_set_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_TX_COEFF_CFG, - C10GB_LT_TX_INC_MAIN_MASK); - break; + C10GB_LT_TX_COEFF_CFG, + C10GB_LT_TX_INC_MAIN_MASK); + break; case POST_TAP: HAL_set_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_TX_COEFF_CFG, - C10GB_LT_TX_INC_POST_MASK); - break; + C10GB_LT_TX_COEFF_CFG, + C10GB_LT_TX_INC_POST_MASK); + break; case PRE_TAP: HAL_set_32bit_reg(this_phy->lt_base_addr, - C10GB_LT_TX_COEFF_CFG, - C10GB_LT_TX_INC_PRE_MASK); - break; + C10GB_LT_TX_COEFF_CFG, + C10GB_LT_TX_INC_PRE_MASK); + break; default: HAL_ASSERT(0); - break; + break; } } -/***************************************************************************//** - calculate the optimal tap setting index based on the PRBS error counts - - sweep the prbs error array to find the minimum error. - - if there are multiple samples that have the same error, determine which of - the minimum samples is closest to the center tap setting +/** + * Please see core10gbasekr_phy_link_training.h for description */ uint32_t -lt_get_optimal_tap_index -( - uint32_t * prbs_arr, - uint32_t prbs_arr_size -) +lt_get_optimal_tap_index(uint32_t *prbs_arr, uint32_t prbs_arr_size) { uint32_t i = 0; uint32_t min_error = prbs_arr[0]; uint32_t min_index = 0; - uint32_t min_midpoint_distance = prbs_arr_size/2; + uint32_t min_midpoint_distance = prbs_arr_size / 2; /* sweep to find min prbs error */ - for(i = 0; i < prbs_arr_size; i++) + for (i = 0; i < prbs_arr_size; i++) { - if(prbs_arr[i] < min_error) + if (prbs_arr[i] < min_error) { min_error = prbs_arr[i]; min_index = i; @@ -520,23 +481,23 @@ lt_get_optimal_tap_index /* sweep to find which index are equal the min, weighted by distance to mid * point of array */ - for(i = 0; i < prbs_arr_size; i++) + for (i = 0; i < prbs_arr_size; i++) { - if(prbs_arr[i] == min_error) + if (prbs_arr[i] == min_error) { - int32_t midpoint_distance = (prbs_arr_size/2) - i; - if(midpoint_distance < 0) + int32_t midpoint_distance = (prbs_arr_size / 2) - i; + if (midpoint_distance < 0) { midpoint_distance *= -1; } - if(midpoint_distance < min_midpoint_distance) + if (midpoint_distance < min_midpoint_distance) { min_midpoint_distance = midpoint_distance; min_index = i; } - if(midpoint_distance == 0) + if (midpoint_distance == 0) { break; } diff --git a/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_link_training.h b/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_link_training.h index 4f9a06c..94bdff6 100644 --- a/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_link_training.h +++ b/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_link_training.h @@ -1,31 +1,14 @@ -/***************************************************************************//** +/** * Copyright 2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * * @file core10gbasekr_phy_link_training.h * @author Microchip FPGA Embedded Systems Solutions - * @brief PHY software configuration + * @brief Core10GBaseKR PHY link training prototypes * */ + #ifndef CORE10GBASEKR_PHY_LINK_TRAINING_H_ #define CORE10GBASEKR_PHY_LINK_TRAINING_H_ @@ -35,192 +18,156 @@ extern "C" { /// @cond @private -#include "phy.h" +#include "core10gbasekr_phy.h" -/***************************************************************************//** - Link partner calibration state machine. - - This function determines which of the link partners transmitter taps are to be - calibrated. - - @param this_phy - The this_phy parameter specifies the 10GBaseKR PHY block. - - @return - This function does not return a value. +/** + * Link partner calibration state machine. + * + * This function determines which of the link partners transmitter taps are to be + * calibrated. + * + * @param this_phy + * The this_phy parameter specifies the 10GBaseKR PHY block. + * + * @return + * This function does not return a value. */ -void -link_partner_calibration_sm -( - phy10gkr_instance_t * this_phy -); - -/***************************************************************************//** - Link partner main (c(0)) cursor sweep. - - The algorithm increments the link partners transmit taps to maximum (as this - algorithm is only used when preset is sent the link partner main tap should be - maximum). When the main tap is maximum the algorithm will decrement the link - partner's main transmit tap to minimum before decrementing the algorithm - stores the PRBS for optimisation. +void link_partner_calibration_sm(phy10gkr_instance_t *this_phy); - When the link partners transmit main tap is minimum algorithm determines the - optimal tap setting based on the PRBS errors stored during sweeping. The - algorithm now increments the link partners transmit tap back to the optimal - tap setting. - - @param this_phy - The this_phy parameter specifies the 10GBaseKR PHY block. - - @return - This function does not return a value. +/** + * Link partner main (c(0)) cursor sweep. + * + * The algorithm increments the link partners transmit taps to maximum (as this + * algorithm is only used when preset is sent the link partner main tap should be + * maximum). When the main tap is maximum the algorithm will decrement the link + * partner's main transmit tap to minimum before decrementing the algorithm + * stores the PRBS for optimisation. + * + * When the link partners transmit main tap is minimum algorithm determines the + * optimal tap setting based on the PRBS errors stored during sweeping. The + * algorithm now increments the link partners transmit tap back to the optimal + * tap setting. + * + * @param this_phy + * The this_phy parameter specifies the 10GBaseKR PHY block. + * + * @return + * This function does not return a value. */ -void -link_partner_main_sweep -( - phy10gkr_instance_t * this_phy -); - -/***************************************************************************//** - Link partner post (c(+1)) cursor sweep. - - The algorithm increments the link partners transmit taps to maximum (as this - algorithm is only used when preset is sent the link partner post tap should be - maximum). When the post tap is maximum the algorithm will decrement the link - partner's post transmit tap to minimum before decrementing the algorithm - stores the PRBS for optimisation. +void link_partner_main_sweep(phy10gkr_instance_t *this_phy); - When the link partners transmit post tap is minimum algorithm determines the - optimal tap setting based on the PRBS errors stored during sweeping. The - algorithm now increments the link partners transmit tap back to the optimal - tap setting. - - @param this_phy - The this_phy parameter specifies the 10GBaseKR PHY block. - - @return - This function does not return a value. +/** + * Link partner post (c(+1)) cursor sweep. + * + * The algorithm increments the link partners transmit taps to maximum (as this + * algorithm is only used when preset is sent the link partner post tap should be + * maximum). When the post tap is maximum the algorithm will decrement the link + * partner's post transmit tap to minimum before decrementing the algorithm + * stores the PRBS for optimisation. + * + * When the link partners transmit post tap is minimum algorithm determines the + * optimal tap setting based on the PRBS errors stored during sweeping. The + * algorithm now increments the link partners transmit tap back to the optimal + * tap setting. + * + * @param this_phy + * The this_phy parameter specifies the 10GBaseKR PHY block. + * + * @return + * This function does not return a value. */ -void -link_partner_post_sweep -( - phy10gkr_instance_t * this_phy -); - -/***************************************************************************//** - Link partner pre (c(-1)) cursor sweep. - - The algorithm increments the link partners transmit taps to maximum (as this - algorithm is only used when preset is sent the link partner pre tap should be - maximum). When the pre tap is maximum the algorithm will decrement the link - partner's pre transmit tap to minimum before decrementing the algorithm - stores the PRBS for optimisation. - - When the link partners transmit pre tap is minimum algorithm determines the - optimal tap setting based on the PRBS errors stored during sweeping. The - algorithm now increments the link partners transmit tap back to the optimal - tap setting. - - Once the link partner's pre tap has incremented back to the optimal setting - the local receiver ready bit is set to indicate to the link partner that - this device is finished calibrating the link partners transmitter taps. - - @param this_phy - The this_phy parameter specifies the 10GBaseKR PHY block. +void link_partner_post_sweep(phy10gkr_instance_t *this_phy); - @return - This function does not return a value. +/** + * Link partner pre (c(-1)) cursor sweep. + * + * The algorithm increments the link partners transmit taps to maximum (as this + * algorithm is only used when preset is sent the link partner pre tap should be + * maximum). When the pre tap is maximum the algorithm will decrement the link + * partner's pre transmit tap to minimum before decrementing the algorithm + * stores the PRBS for optimisation. + * + * When the link partners transmit pre tap is minimum algorithm determines the + * optimal tap setting based on the PRBS errors stored during sweeping. The + * algorithm now increments the link partners transmit tap back to the optimal + * tap setting. + * + * Once the link partner's pre tap has incremented back to the optimal setting + * the local receiver ready bit is set to indicate to the link partner that + * this device is finished calibrating the link partners transmitter taps. + * + * @param this_phy + * The this_phy parameter specifies the 10GBaseKR PHY block. + * + * @return + * This function does not return a value. */ -void -link_partner_pre_sweep -( - phy10gkr_instance_t * this_phy -); - -/***************************************************************************//** - This function sets the decrement bit of a specific transmit equalizer tap - register which updates the transmitted coefficient update to the link partner. - - @param this_phy - The this_phy parameter specifies the 10GBaseKR PHY block. - - @param tap_type - This enumeration specifies the which transmitter tap will be decremented +void link_partner_pre_sweep(phy10gkr_instance_t *this_phy); - @return - This function does not return a value. +/** + * This function sets the decrement bit of a specific transmit equalizer tap + * register which updates the transmitted coefficient update to the link partner. + * + * @param this_phy + * The this_phy parameter specifies the 10GBaseKR PHY block. + * + * @param tap_type + * This enumeration specifies the which transmitter tap will be decremented + * + * @return + * This function does not return a value. */ -void -lt_tap_decrement -( - phy10gkr_instance_t * this_phy, - phy10gkr_tx_equalizer_tap_t tap_type -); - -/***************************************************************************//** - This function sets the hold bit of a specific transmit equalizer tap - register which updates the transmitted coefficient update to the link partner. +void lt_tap_decrement(phy10gkr_instance_t *this_phy, phy10gkr_tx_equalizer_tap_t tap_type); - @param this_phy - The this_phy parameter specifies the 10GBaseKR PHY block. - - @param tap_type - This enumeration specifies the which transmitter tap will be held - - @return - This function does not return a value. +/** + * This function sets the hold bit of a specific transmit equalizer tap + * register which updates the transmitted coefficient update to the link partner. + * + * @param this_phy + * The this_phy parameter specifies the 10GBaseKR PHY block. + * + * @param tap_type + * This enumeration specifies the which transmitter tap will be held + * + * @return + * This function does not return a value. */ -void -lt_tap_hold -( - phy10gkr_instance_t * this_phy, - phy10gkr_tx_equalizer_tap_t tap_type -); - -/***************************************************************************//** - This function sets the increment bit of a specific transmit equalizer tap - register which updates the transmitted coefficient update to the link partner. - - @param this_phy - The this_phy parameter specifies the 10GBaseKR PHY block. - - @param tap_type - This enumeration specifies the which transmitter tap will be incremented +void lt_tap_hold(phy10gkr_instance_t *this_phy, phy10gkr_tx_equalizer_tap_t tap_type); - @return - This function does not return a value. +/** + * This function sets the increment bit of a specific transmit equalizer tap + * register which updates the transmitted coefficient update to the link partner. + * + * @param this_phy + * The this_phy parameter specifies the 10GBaseKR PHY block. + * + * @param tap_type + * This enumeration specifies the which transmitter tap will be incremented + * + * @return + * This function does not return a value. */ -void -lt_tap_increment -( - phy10gkr_instance_t * this_phy, - phy10gkr_tx_equalizer_tap_t tap_type -); - -/***************************************************************************//** - This function calculates the optimal tap setting index based on the PRBS error - counts stored during maximum to minimum tap sweep. +void lt_tap_increment(phy10gkr_instance_t *this_phy, phy10gkr_tx_equalizer_tap_t tap_type); - Sweeps the PRBS error array to find the minimum error, if there are multiple - samples that have the same error a weighting is applied to select the tap - setting closest to the center tap setting. - - @param prbs_arr - This is a pointer to the first sample of the PRBS error sample array - - @param prbs_arr_size - This identifies the number of samples. - - @return - This function returns the number of increments required to increment a tap - to its optimal tap setting. +/** + * This function calculates the optimal tap setting index based on the PRBS error + * counts stored during maximum to minimum tap sweep. + * + * Sweeps the PRBS error array to find the minimum error, if there are multiple + * samples that have the same error a weighting is applied to select the tap + * setting closest to the center tap setting. + * + * @param prbs_arr + * This is a pointer to the first sample of the PRBS error sample array + * + * @param prbs_arr_size + * This identifies the number of samples. + * + * @return + * This function returns the number of increments required to increment a tap + * to its optimal tap setting. */ -uint32_t -lt_get_optimal_tap_index -( - uint32_t * prbs_arr, - uint32_t prbs_arr_size -); +uint32_t lt_get_optimal_tap_index(uint32_t *prbs_arr, uint32_t prbs_arr_size); /// @endcond diff --git a/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_reg.h b/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_reg.h index 6f0a29a..96f7ffb 100644 --- a/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_reg.h +++ b/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_reg.h @@ -1,1284 +1,1249 @@ -/***************************************************************************//** - * Copyright 2022 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * - * @file core10gbasekr_phy_reg.h - * @author Microchip FPGA Embedded Systems Solutions - * @brief Core10GBaseKR PHY memory map - * - */ - -#ifndef CORE10GBASEKR_PHY_REG_H_ -#define CORE10GBASEKR_PHY_REG_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/// @cond @private - -#include "uint_32_bit_masks.h" - -#define __I const volatile -#define __O volatile -#define __IO volatile - -/******************************************************************************/ -/* Core10GBaseKR PHY Clause 73 (Auto Negotiation) */ -/******************************************************************************/ - -/*------------------------------------------------------------------------------ - * AN_CONTROL register details - */ -#define C10GB_AN_CONTROL_REG_OFFSET (0x0U << 2U) - -/* - * Auto Negotiation Restart - * - * Restart_negotiation. Self clears, and always reads as 0. - */ -#define C10GB_AN_RESTART_OFFSET C10GB_AN_CONTROL_REG_OFFSET -#define C10GB_AN_RESTART_MASK MASK_BIT_9 -#define C10GB_AN_RESTART_SHIFT (9U) - -/* - * Auto Negotiation Enable - * - * Auto-negotiation Enable. Writing “1” in this register enables - * auto-negotiation - */ -#define C10GB_AN_ENABLE_OFFSET C10GB_AN_CONTROL_REG_OFFSET -#define C10GB_AN_ENABLE_MASK MASK_BIT_12 -#define C10GB_AN_ENABLE_SHIFT (12U) - -/* - * Auto Negotiation Reset - * - * Main_reset. Self clears. When reads as 0 the reset is complete. - */ -#define C10GB_AN_RESET_OFFSET C10GB_AN_CONTROL_REG_OFFSET -#define C10GB_AN_RESET_MASK MASK_BIT_15 -#define C10GB_AN_RESET_SHIFT (15U) - - -/*------------------------------------------------------------------------------ - * AN_STATUS register details - */ -#define C10GB_AN_STATUS_REG_OFFSET (0x1U << 2U) - -/* - * Auto Negotiation Able - * - * If “1” indicates that Link Partner is Autonegotiation Able - */ -#define C10GB_AN_CAPABLE_OFFSET C10GB_AN_STATUS_REG_OFFSET -#define C10GB_AN_CAPABLE_MASK MASK_BIT_0 -#define C10GB_AN_CAPABLE_SHIFT (0U) - -/* - * Auto Negotiation Support - * - * If “1” indicates that Autonegotiation is supported - */ -#define C10GB_AN_SUPPORT_OFFSET C10GB_AN_STATUS_REG_OFFSET -#define C10GB_AN_SUPPORT_MASK MASK_BIT_3 -#define C10GB_AN_SUPPORT_SHIFT (3U) - -/* - * Auto Negotiation Complete - * - * If “1” indicates that AN is complete - */ -#define C10GB_AN_COMPLETE_OFFSET C10GB_AN_STATUS_REG_OFFSET -#define C10GB_AN_COMPLETE_MASK MASK_BIT_5 -#define C10GB_AN_COMPLETE_SHIFT (5U) - -/* - * Auto Negotiation Page Received - * - * Page_RX. If “1” that Page is received from the link partner. Clear on read - */ -#define C10GB_AN_PAGE_RX_OFFSET C10GB_AN_STATUS_REG_OFFSET -#define C10GB_AN_PAGE_RX_MASK MASK_BIT_6 -#define C10GB_AN_PAGE_RX_SHIFT (6U) - -/* - * Auto Negotiation Parallel Fault Detected - * - * Parallel_Detect_fault. Clear on read - */ -#define C10GB_AN_PARALLEL_DETECT_OFFSET C10GB_AN_STATUS_REG_OFFSET -#define C10GB_AN_PARALLEL_DETECT_MASK MASK_BIT_9 -#define C10GB_AN_PARALLEL_DETECT_SHIFT (9U) - -/* - * Auto Negotiation State Variable - * - * This register returns the state variables of the Auto-Negotiation. - * ST_AUTO_NEG_ENABLE = 0x0; - * ST_TRANSMIT_DISABLE = 0x1; - * ST_CAPABILITY_DETECT = 0x2; - * ST_ACKNOWLEDGE_DETECT = 0x3; - * ST_COMPLETE_ACKNOWLE = 0x4; - * ST_AN_GOOD_CHECK = 0x5; - * ST_AN_GOOD = 0x6; - * ST_NEXT_PAGE_WAIT = 0x7; - * ST_NEXT_PAGE_WAIT_TX_IDLE = 0x8; - * ST_LINK_STATUS_CHECK = 0x9; - * ST_PARALLEL_DETECTION_FAULT = 0xA; - */ -#define C10GB_AN_STATE_OFFSET C10GB_AN_STATUS_REG_OFFSET -#define C10GB_AN_STATE_SHIFT (12U) -#define C10GB_AN_STATE_MASK BIT_MASK_4_BITS << \ - C10GB_AN_STATE_SHIFT - - -/*------------------------------------------------------------------------------ - * MR_ADV_CAPABILITY_1 Bits [16:1] - * - * This register gives the value of the bits 16:1 of the Advertisement Ability - * Register - * Bits [4:0] - Selector Field (S[4:0]) is a five-bit wide field, encoding 32 - * possible messages. Selector Field encoding definitions are shown in Annex - * 28A of the IEEE 802.3 specification - * Bits[9:5] -Echoed Nonce Field (E[4:0]) is a 5-bit wide field containing - * the nonce received from the link partner - * Bits[12:10] - Pause Encoding as defined in Annexure 28B of the IEEE 802.3 - * specification - * Bit 13 - Remote Fault (RF) of the base link codeword. The default value is - * logical zero - * Bit 14 -Acknowledge (Ack) is used by the Auto-Negotiation function to - * indicate that a device has successfully received its link partner’s link - * codeword. - * Bit 15 -Next Page (NP) bit. Support of Next Pages is mandatory. If the - * device does not have any Next Pages to send, the NP bit shall be set to - * logical zero - */ -#define C10GB_AN_MR_ADV_CAPABILITY_1_REG_OFFSET \ - (0x10U << 2U) - - - -/*------------------------------------------------------------------------------ - * MR_ADV_CAPABILITY_2 Bits [32:17] - * - * This register gives the value of the bits 32:17 of the Advertisement Ability - * Register - * Bits[20:16] – Transmitted Nonce Field - * Bits[31:21] – Technology Ability Field bits[ 10:0] . Technology Ability - * Field is a 25-bit wide field containing information indicating supported - * technologies specific to the selector field value when used with the - * Auto-Negotiation for Backplane Ethernet. - */ -#define C10GB_AN_MR_ADV_CAPABILITY_2_REG_OFFSET \ - (0x11U << 2U) - - -/*------------------------------------------------------------------------------ - * MR_ADV_CAPABILITY_3 Bits [48:33] - * - * This register gives the value of the bits 48:33 of the Advertisement Ability - * Register - * Bits [45:32] – Technology Ability Field bits[ 25:11]. For Technology Ability - * Field encoding refer to Table 73-4 of the IEEE specification - * Bits [47:46] - FEC Capability (FEC Not supported in current implementation). - * Bit 46 - FEC ability, if set to ‘1’ PHY has FEC Ability - * Bit 47 - FEC requested When the FEC requested bit is set to logical one, it - * indicates a request to enable FEC on the link. - */ -#define C10GB_AN_MR_ADV_CAPABILITY_3_REG_OFFSET \ - (0x12U << 2U) - - -/* - * Adevertisment Ability Registers Details - */ -#define C10GB_AN_ADV_CAPABILITY_SHIFT (0U) -#define C10GB_AN_ADV_CAPABILITY_MASK BIT_MASK_16_BITS << \ - C10GB_AN_ADV_CAPABILITY_SHIFT - - -/*------------------------------------------------------------------------------ - * MR_LP_BASE_PAGE_CAPABILITY_1 Bits [16:1] - * - * This register gives the value of the bits 16:1 of the Link Partner Base Page - * Ability Register. The bits definition are same as Advertisement ability - * register -1 - */ -#define C10GB_AN_MR_LP_BASE_PG_CAPABILITY_1_REG_OFFSET \ - (0x13U << 2U) - - -/*------------------------------------------------------------------------------ - * MR_LP_BASE_PAGE_CAPABILITY_2 Bits [32:17] - * - * This register gives the value of the bits 32:17 of the Link Partner Base Page - * Ability Register. The bits definition are same as Advertisement ability - * register -2 - */ -#define C10GB_AN_MR_LP_BASE_PG_CAPABILITY_2_REG_OFFSET \ - (0x14U << 2U) - - -/*------------------------------------------------------------------------------ - * MR_LP_BASE_PAGE_CAPABILITY_3 Bits [48:33] - * - * This register gives the value of the bits 48:33 of the Link Partner Base Page - * Ability Register. The bits definition are same as Advertisement ability - * register -3 - * - */ -#define C10GB_AN_MR_LP_BASE_PG_CAPABILITY_3_REG_OFFSET \ - (0x15U << 2U) - -/* - * Link Partner Base Page Ability Registers Details - */ -#define C10GB_AN_LP_BASE_PAGE_CAPABILITY_SHIFT (0U) -#define C10GB_AN_LP_BASE_PAGE_CAPABILITY_MASK BIT_MASK_16_BITS << \ - C10GB_AN_LP_BASE_PAGE_CAPABILITY_SHIFT - -/*------------------------------------------------------------------------------ - * MR_XNP_TRANSMIT_1 Bits [16:1] - * - * This register gives the value of the bits 16:1 of the XNP(next page)Transmit - * Register. - * Bit[10:0] – Message Code Field (M[10:0]) is an eleven bit wide field, - * encoding 2048 possible messages. Message Code Field definitions are shown in - * Annex 28C of the IEEE 802.3 specification - * Bit 11 – Toggle (T) is used by the Arbitration function to ensure - * synchronization with the Link Partner during Next Page exchange. This bit - * shall always take the opposite value of the Toggle bit in the previously - * exchanged link codeword - * Bit 12 – Acknowledge 2 (Ack2) is used by the Next Page function to indicate - * that a device has the ability to comply with the message. Ack2 shall be set - * as follows: - * 0 - cannot comply with message - * 1 - will comply with message - * Bit 13 – Message Page bit - * 0 – Unformatted Page - * 1 – Message Page - * Bit 14 – Acknowledge. Acknowledge (Ack) is used by the Auto-Negotiation - * function to indicate that a device has successfully received its Link - * Partner’s link codeword - * Bit 15 - Next Page Bit - * 0 - last page - * 1 - additional Next Page(s) will follow - */ -#define C10GB_AN_MR_XNP_TRANSMIT_1_REG_OFFSET (0x16U << 2U) - - -/*------------------------------------------------------------------------------ - * MR_XNP_TRANSMIT_2 Bits [32:17] - * - * This register gives the value of the bits 32:17 of the XNP Transmit Register. - * This value corresponds to the Bits[31:16] of the Unformatted Code Field of - * the Next Page Register. - */ -#define C10GB_AN_MR_XNP_TRANSMIT_2_REG_OFFSET (0x17U << 2U) - - -/*------------------------------------------------------------------------------ - * MR_XNP_TRANSMIT_3 Bits [48:33] - * - * This register gives the value of the bits 48:33 of the XNP Transmit Register. - * This value corresponds to the Bits[47:32] of the Unformatted Code Field of - * the Next Page Register. - */ -#define C10GB_AN_MR_XNP_TRANSMIT_3_REG_OFFSET (0x18U << 2U) - -/* - * XNP Transmit Registers Details - */ -#define C10GB_AN_XNP_TRANSMIT_SHIFT (0U) -#define C10GB_AN_XNP_TRANSMIT_MASK BIT_MASK_16_BITS << \ - C10GB_AN_XNP_TRANSMIT_SHIFT - -/*------------------------------------------------------------------------------ - * LP_XNP_CAPABILITY_1 Bits [16:1] - * - * This register gives the value of the bits 16:1 of the Link Partner next page - * Ability register. The bits definition are same as XNP Transmit register -1 - */ -#define C10GB_AN_LP_XNP_CAPABILITY_1_REG_OFFSET \ - (0x19U << 2U) - - -/*------------------------------------------------------------------------------ - * LP_XNP_CAPABILITY_2 Bits [32:17] - * - * This register gives the value of the bits 32:17 of the Link Partner next page - * Ability register. The bits definition are same as XNP Transmit register -2 - */ -#define C10GB_AN_LP_XNP_CAPABILITY_2_REG_OFFSET \ - (0x1aU << 2U) - - -/*------------------------------------------------------------------------------ - * LP_XNP_CAPABILITY_3 Bits [48:33] - * - * This register gives the value of the bits 48:33 of the Link Partner next page - * Ability register. The bits definition are same as XNP Transmit register -3 - */ -#define C10GB_AN_LP_XNP_CAPABILITY_3_REG_OFFSET \ - (0x1bU << 2U) - -/* - * Link Partner Next Page Ability Registers Details - */ -#define C10GB_AN_LP_XNP_CAPABILITY_SHIFT (0U) -#define C10GB_AN_LP_XNP_CAPABILITY_MASK BIT_MASK_16_BITS << \ - C10GB_AN_LP_XNP_CAPABILITY_SHIFT - -/*------------------------------------------------------------------------------ - * AN Link Fail Inhibit Timer - * - * An_link_fail_inhibit_timer is 500ms timer which starts incrementing in - * AN GOOD CHECK state (This state is indication of AN completion) and if it - * elapses in during this state then the Auto negotiation process starts again - */ -#define C10GB_AN_LINK_FAIL_INHIBIT_TIMER_REG_OFFSET \ - (0x0dU << 2U) - -/******************************************************************************/ -/* Core10GBaseKR PHY Clause 72 (Link Training) */ -/******************************************************************************/ - -/*------------------------------------------------------------------------------ - * Link Training Control Register - */ -#define C10GB_LT_CTRL_REG_OFFSET (0x0U << 2U) - -/* - * Link Training Initialize - * - * If “1” initialize coefficient is transmitted to the link partner - */ -#define C10GB_LT_INIT_OFFSET C10GB_LT_CTRL_REG_OFFSET -#define C10GB_LT_INIT_SHIFT (3U) -#define C10GB_LT_INIT_MASK MASK_BIT_3 - -/* - * Link Training Preset - * - * If “1” preset coefficient is transmitted to the link partner - */ -#define C10GB_LT_PRESET_OFFSET C10GB_LT_CTRL_REG_OFFSET -#define C10GB_LT_PRESET_SHIFT (2U) -#define C10GB_LT_PRESET_MASK MASK_BIT_2 - -/* - * Link Restart Training - * - * A write of “1” to this field brings the link training IP in reset mode. - * To bring the Link training IP out of reset, write a value of 0x0 into this - * register - */ -#define C10GB_LT_RESTART_TRAINING_OFFSET C10GB_LT_CTRL_REG_OFFSET -#define C10GB_LT_RESTART_TRAINING_SHIFT (1U) -#define C10GB_LT_RESTART_TRAINING_MASK MASK_BIT_1 - -/* - * Link Training Enable - * - * If “1” enables the link training. This bit should be enabled from the - * software after the AN_GOOD_CHK interrupt is received by the Firmware - */ -#define C10GB_LT_RESTART_EN_OFFSET C10GB_LT_CTRL_REG_OFFSET -#define C10GB_LT_RESTART_EN_SHIFT (0U) -#define C10GB_LT_RESTART_EN_MASK MASK_BIT_0 - -/*------------------------------------------------------------------------------ - * Max Wait Timer Configuration - * - * The value in the MAX wait timer should be configured to 500ms, the training - * state diagram enters into the training failure state once the timer reaches - * 500ms. - */ -#define C10GB_LT_MAX_WAIT_TIMER_REG_OFFSET (0x1U << 2U) - -#define C10GB_LT_MAX_WAIT_TIMER_OFFSET C10GB_LT_MAX_WAIT_TIMER_REG_OFFSET -#define C10GB_LT_MAX_WAIT_TIMER_SHIFT (0U) -#define C10GB_LT_MAX_WAIT_TIMER_MASK BIT_MASK_32_BITS << \ - C10GB_LT_MAX_WAIT_TIMER_SHIFT - -/*------------------------------------------------------------------------------ - * Frame WAIT Timer Configuration Register - * - * The value in the frame WAIT Timer register should be between 100 to 300 - * frames. The default value is configured to 100 frames. - */ -#define C10GB_LT_FRM_WAIT_TIMER_REG_OFFSET (0x2U << 2U) - -#define C10GB_LT_FRM_WAIT_TIMER_OFFSET C10GB_LT_FRM_WAIT_TIMER_REG_OFFSET -#define C10GB_LT_FRM_WAIT_TIMER_SHIFT (0U) -#define C10GB_LT_FRM_WAIT_TIMER_MASK BIT_MASK_32_BITS << \ - C10GB_LT_FRM_WAIT_TIMER_SHIFT - -/*------------------------------------------------------------------------------ - * Preset MAIN-TAP Configuration Register - * - * The value in this register gives the main TAP value, when the preset - * Coefficient is received from the Link Partner. The Link Training Algorithm - * starts from this TAP value. - */ -#define C10GB_LT_PRESET_MAIN_TAP_REG_OFFSET (0x3U << 2U) - -#define C10GB_LT_PRESET_MAIN_TAP_OFFSET C10GB_LT_PRESET_MAIN_TAP_REG_OFFSET -#define C10GB_LT_PRESET_MAIN_TAP_SHIFT (0U) -#define C10GB_LT_PRESET_MAIN_TAP_MASK BIT_MASK_16_BITS << \ - C10GB_LT_PRESET_MAIN_TAP_SHIFT - -/*------------------------------------------------------------------------------ - * Preset Post-TAP Configuration Register - * - * The value in this register gives the post-TAP value when the preset - * Coefficient is received from the Link Partner. The Link Training Algorithm - * starts from this TAP value. - */ -#define C10GB_LT_PRESET_POST_TAP_REG_OFFSET (0x4U << 2U) - -#define C10GB_LT_PRESET_POST_TAP_OFFSET C10GB_LT_PRESET_POST_TAP_REG_OFFSET -#define C10GB_LT_PRESET_POST_TAP_SHIFT (0U) -#define C10GB_LT_PRESET_POST_TAP_MASK BIT_MASK_16_BITS << \ - C10GB_LT_PRESET_POST_TAP_SHIFT - -/*------------------------------------------------------------------------------ - * Preset Pre-TAP Configuration Register - * - * The value in this register gives the pre-TAP when the preset Coefficient is - * received from the Link Partner. The Link Training Algorithm starts from this - * TAP value. - */ -#define C10GB_LT_PRESET_PRE_TAP_REG_OFFSET (0x5U << 2U) - -#define C10GB_LT_PRESET_PRE_TAP_OFFSET C10GB_LT_PRESET_PRE_TAP_REG_OFFSET -#define C10GB_LT_PRESET_PRE_TAP_SHIFT (0U) -#define C10GB_LT_PRESET_PRE_TAP_MASK BIT_MASK_16_BITS << \ - C10GB_LT_PRESET_PRE_TAP_SHIFT - -/*------------------------------------------------------------------------------ - * Initialize MAIN-TAP Configuration Register - * - * The value in this register gives the main TAP value, when the Initialize - * Coefficient is received from the Link Partner. - */ -#define C10GB_LT_INIT_MAIN_TAP_REG_OFFSET (0x6U << 2U) - -#define C10GB_LT_INIT_MAIN_TAP_OFFSET C10GB_LT_INIT_MAIN_TAP_REG_OFFSET -#define C10GB_LT_INIT_MAIN_TAP_SHIFT (0U) -#define C10GB_LT_INIT_MAIN_TAP_MASK BIT_MASK_16_BITS << \ - C10GB_LT_INIT_MAIN_TAP_SHIFT - -/*------------------------------------------------------------------------------ - * Initialize Post-TAP Configuration Register - * - * The value in this register gives the post-TAP value when the Initialize - * Coefficient is received from the Link Partner. - */ -#define C10GB_LT_INIT_POST_TAP_REG_OFFSET (0x7U << 2U) - -#define C10GB_LT_INIT_POST_TAP_OFFSET C10GB_LT_INIT_POST_TAP_REG_OFFSET -#define C10GB_LT_INIT_POST_TAP_SHIFT (0U) -#define C10GB_LT_INIT_POST_TAP_MASK BIT_MASK_16_BITS << \ - C10GB_LT_INIT_POST_TAP_SHIFT - -/*------------------------------------------------------------------------------ - * Initialize Pre-TAP Configuration Register - * - * The value in this register gives the pre-TAP when the Initialize Coefficient - * is received from the Link Partner. - */ -#define C10GB_LT_INIT_PRE_TAP_REG_OFFSET (0x8U << 2U) - -#define C10GB_LT_INIT_PRE_TAP_OFFSET C10GB_LT_INIT_PRE_TAP_REG_OFFSET -#define C10GB_LT_INIT_PRE_TAP_SHIFT (0U) -#define C10GB_LT_INIT_PRE_TAP_MASK BIT_MASK_16_BITS << \ - C10GB_LT_INIT_PRE_TAP_SHIFT - -/*------------------------------------------------------------------------------ - * Maximum Coefficient Limit of Main Tap Configuration Register - * - * The value in this register gives the Maximum value of the main TAP setting - * which will be tested for the TX equalization for the optimum main tap - * settings. - */ -#define C10GB_LT_MAX_MAIN_TAP_REG_OFFSET (0x9U << 2U) - -#define C10GB_LT_MAX_MAIN_TAP_OFFSET C10GB_LT_MAX_MAIN_TAP_REG_OFFSET -#define C10GB_LT_MAX_MAIN_TAP_SHIFT (0U) -#define C10GB_LT_MAX_MAIN_TAP_MASK BIT_MASK_16_BITS << \ - C10GB_LT_MAX_MAIN_TAP_SHIFT - -/*------------------------------------------------------------------------------ - * Minimum Coefficient Limit of Main Tap Configuration Register - * - * The value in this register gives the minimum value of the main TAP setting - * which will be tested for the TX equalization for the optimum main tap - * settings. - */ -#define C10GB_LT_MIN_MAIN_TAP_REG_OFFSET (0xAU << 2U) - -#define C10GB_LT_MIN_MAIN_TAP_OFFSET C10GB_LT_MIN_MAIN_TAP_REG_OFFSET -#define C10GB_LT_MIN_MAIN_TAP_SHIFT (0U) -#define C10GB_LT_MIN_MAIN_TAP_MASK BIT_MASK_16_BITS << \ - C10GB_LT_MIN_MAIN_TAP_SHIFT - -/*------------------------------------------------------------------------------ - * Maximum Coefficient Limit of Post Tap Configuration Register - * - * The value in this register gives the Maximum value of the post TAP setting - * which will be tested for the TX equalization for the optimum post tap - * settings. - */ -#define C10GB_LT_MAX_POST_TAP_REG_OFFSET (0xBU << 2U) - -#define C10GB_LT_MAX_POST_TAP_OFFSET C10GB_LT_MAX_POST_TAP_REG_OFFSET -#define C10GB_LT_MAX_POST_TAP_SHIFT (0U) -#define C10GB_LT_MAX_POST_TAP_MASK BIT_MASK_16_BITS << \ - C10GB_LT_MAX_POST_TAP_SHIFT - -/*------------------------------------------------------------------------------ - * Minimum Coefficient Limit of Post Tap Configuration Register - * - * The value in this register gives the minimum value of the post TAP setting - * which will be tested for the TX equalization for the optimum post tap - * settings. - */ -#define C10GB_LT_MIN_POST_TAP_REG_OFFSET (0xCU << 2U) - -#define C10GB_LT_MIN_POST_TAP_OFFSET C10GB_LT_MIN_POST_TAP_REG_OFFSET -#define C10GB_LT_MIN_POST_TAP_SHIFT (0U) -#define C10GB_LT_MIN_POST_TAP_MASK BIT_MASK_16_BITS << \ - C10GB_LT_MIN_POST_TAP_SHIFT - -/*------------------------------------------------------------------------------ - * Maximum Coefficient Limit of Pre Tap Configuration Register - * - * The value in this register gives the Maximum value of the pre TAP setting - * which will be tested for the TX equalization for the optimum pre tap - * settings. - */ -#define C10GB_LT_MAX_PRE_TAP_REG_OFFSET (0xDU << 2U) - -#define C10GB_LT_MAX_PRE_TAP_OFFSET C10GB_LT_MAX_PRE_TAP_REG_OFFSET -#define C10GB_LT_MAX_PRE_TAP_SHIFT (0U) -#define C10GB_LT_MAX_PRE_TAP_MASK BIT_MASK_16_BITS << \ - C10GB_LT_MAX_PRE_TAP_SHIFT - -/*------------------------------------------------------------------------------ - * Minimum Coefficient Limit of Pre Tap Configuration Register - * - * The value in this register gives the minimum value of the pre TAP setting - * which will be tested for the TX equalization for the optimum pre tap - * settings. - */ -#define C10GB_LT_MIN_PRE_TAP_REG_OFFSET (0xEU << 2U) - -#define C10GB_LT_MIN_PRE_TAP_OFFSET C10GB_LT_MIN_PRE_TAP_REG_OFFSET -#define C10GB_LT_MIN_PRE_TAP_SHIFT (0U) -#define C10GB_LT_MIN_PRE_TAP_MASK BIT_MASK_16_BITS << \ - C10GB_LT_MIN_PRE_TAP_SHIFT - -/*------------------------------------------------------------------------------ - * TX Equalization Register - */ -#define C10GB_LT_TX_EQUAL_REG_OFFSET (0xFU << 2U) - -/* - * TX Equalization Pre Tap Done - * - * A write to “1” in this field indicates that that tx_equalization is done for - * the PRE TAP - */ -#define C10GB_LT_TX_EQUAL_PRE_DONE_OFFSET C10GB_LT_TX_EQUAL_REG_OFFSET -#define C10GB_LT_TX_EQUAL_PRE_DONE_SHIFT (3U) -#define C10GB_LT_TX_EQUAL_PRE_DONE_MASK MASK_BIT_3 - -/* - * TX Equalization Post Tap Done - * - * A write to “1” in this field indicates that that tx_equalization is done for - * the post TAP - */ -#define C10GB_LT_TX_EQUAL_POST_DONE_OFFSET C10GB_LT_TX_EQUAL_REG_OFFSET -#define C10GB_LT_TX_EQUAL_POST_DONE_SHIFT (2U) -#define C10GB_LT_TX_EQUAL_POST_DONE_MASK MASK_BIT_2 - -/* - * TX Equalization Main Tap Done - * - * A write to “1” in this field indicates that that tx_equalization is done for - * the main TAP - */ -#define C10GB_LT_TX_EQUAL_MAIN_DONE_OFFSET C10GB_LT_TX_EQUAL_REG_OFFSET -#define C10GB_LT_TX_EQUAL_MAIN_DONE_SHIFT (1U) -#define C10GB_LT_TX_EQUAL_MAIN_DONE_MASK MASK_BIT_1 - -/* - * TX Equalization Done - * - * A write to “1” in this field indicates that that tx_equalization is done for - * all the TAPs (pre, post and main) - */ -#define C10GB_LT_TX_EQUAL_DONE_OFFSET C10GB_LT_TX_EQUAL_REG_OFFSET -#define C10GB_LT_TX_EQUAL_DONE_SHIFT (0U) -#define C10GB_LT_TX_EQUAL_DONE_MASK MASK_BIT_0 - -/*------------------------------------------------------------------------------ - * Local Receiver Lock Register - */ -#define C10GB_LT_LOCAL_RCVR_LOCK_REG_OFFSET (0x10U << 2U) - -/* - * Local Receiver Locked - * - * Write “1” to this register from the software once the local receiver is - * ready - */ -#define C10GB_LT_LOCAL_RCVR_LOCKED_OFFSET C10GB_LT_LOCAL_RCVR_LOCK_REG_OFFSET -#define C10GB_LT_LOCAL_RCVR_LOCKED_SHIFT (0U) -#define C10GB_LT_LOCAL_RCVR_LOCKED_MASK MASK_BIT_0 - -/*------------------------------------------------------------------------------ - * TX New Main Tap Register - */ -#define C10GB_LT_TX_NEW_MAIN_TAP_REG_OFFSET (0x11U << 2U) - -/* - * TX New Main Tap - * - * A value in this register gives the value of the new main tap value, which - * is used to update the TX equalization SerDes registers. - */ -#define C10GB_LT_TX_NEW_MAIN_TAP_OFFSET C10GB_LT_TX_NEW_MAIN_TAP_REG_OFFSET -#define C10GB_LT_TX_NEW_MAIN_TAP_SHIFT (0U) -#define C10GB_LT_TX_NEW_MAIN_TAP_MASK BIT_MASK_8_BITS << \ - C10GB_LT_TX_NEW_MAIN_TAP_SHIFT - -/*------------------------------------------------------------------------------ - * TX New Post Tap Register - */ -#define C10GB_LT_TX_NEW_POST_TAP_REG_OFFSET (0x12U << 2U) - -/* - * TX New Post Tap - * - * A value in this register gives the value of the new Post tap value, which - * is used to update the TX equalization SerDes registers. - */ -#define C10GB_LT_TX_NEW_POST_TAP_OFFSET C10GB_LT_TX_NEW_POST_TAP_REG_OFFSET -#define C10GB_LT_TX_NEW_POST_TAP_SHIFT (0U) -#define C10GB_LT_TX_NEW_POST_TAP_MASK BIT_MASK_8_BITS << \ - C10GB_LT_TX_NEW_POST_TAP_SHIFT - -/*------------------------------------------------------------------------------ - * TX New Pre Tap Register - */ -#define C10GB_LT_TX_NEW_PRE_TAP_REG_OFFSET (0x13U << 2U) - -/* - * TX New Pre Tap - * - * A value in this register gives the value of the new Pre tap value, which is - * used to update the TX equalization SerDes registers. - */ -#define C10GB_LT_TX_NEW_PRE_TAP_OFFSET C10GB_LT_TX_NEW_PRE_TAP_REG_OFFSET -#define C10GB_LT_TX_NEW_PRE_TAP_SHIFT (0U) -#define C10GB_LT_TX_NEW_PRE_TAP_MASK BIT_MASK_8_BITS << \ - C10GB_LT_TX_NEW_PRE_TAP_SHIFT - -/*------------------------------------------------------------------------------ - * Training State Machine Status - */ -#define C10GB_LT_TRAINING_SM_STATUS_REG_OFFSET (0x14U << 2U) - -/* - * Remote Receiver Ready - * - * If “1” it indicates that remote receiver is ready - */ -#define C10GB_LT_REMOTE_TRAINED_OFFSET C10GB_LT_TRAINING_SM_STATUS_REG_OFFSET -#define C10GB_LT_REMOTE_TRAINED_SHIFT (4U) -#define C10GB_LT_REMOTE_TRAINED_MASK MASK_BIT_4 - -/* - * Link Up - * - * If “1” it indicates that Link is ready - */ -#define C10GB_LT_LINK_UP_OFFSET C10GB_LT_TRAINING_SM_STATUS_REG_OFFSET -#define C10GB_LT_LINK_UP_SHIFT (3U) -#define C10GB_LT_LINK_UP_MASK MASK_BIT_3 - -/* - * Training State Machine - * - * The value in this register gives the current values of the training state - * machine. - * IDLE = 3'b000 - * INITIALIZE = 3'b001 - * SEND_TRAINING = 3'b011 - * TRAIN_LOCAL = 3'b010 - * TRAIN_REMOTE = 3'b110 - * LINK_READY = 3'b111 - * SEND_DATA = 3'b101 - * RAINING_FAILURE = 3'b100 - - */ -#define C10GB_LT_TRAINING_SM_OFFSET C10GB_LT_TRAINING_SM_STATUS_REG_OFFSET -#define C10GB_LT_TRAINING_SM_SHIFT (0U) -#define C10GB_LT_TRAINING_SM_MASK BIT_MASK_2_BITS << \ - C10GB_LT_TRAINING_SM_SHIFT - -/*------------------------------------------------------------------------------ - * TX Updated Status Register - */ -#define C10GB_LT_TX_UPDATED_STATUS_REG_OFFSET (0x15U << 2U) - -/* - * Tx Updated Status Pre Tap - * - * A value in this register gives the value of the current status transmitted - * to the link partner for the pre Tap - * 1 1 = maximum - * 1 0 = minimum - * 0 1 = updated - * 0 0 = not_updated - */ -#define C10GB_LT_TX_UPDATED_STAT_PRE_OFFSET C10GB_LT_TX_UPDATED_STATUS_REG_OFFSET -#define C10GB_LT_TX_UPDATED_STAT_PRE_SHIFT (16U) -#define C10GB_LT_TX_UPDATED_STAT_PRE_MASK BIT_MASK_2_BITS << \ - C10GB_LT_TX_UPDATED_STAT_PRE_SHIFT - -/* - * Tx Updated Status Post Tap - * - * A value in this register gives the value of the current status transmitted - * to the link partner for the post Tap - * 1 1 = maximum - * 1 0 = minimum - * 0 1 = updated - * 0 0 = not_updated - */ -#define C10GB_LT_TX_UPDATED_STAT_POST_OFFSET C10GB_LT_TX_UPDATED_STATUS_REG_OFFSET -#define C10GB_LT_TX_UPDATED_STAT_POST_SHIFT (14U) -#define C10GB_LT_TX_UPDATED_STAT_POST_MASK BIT_MASK_2_BITS << \ - C10GB_LT_TX_UPDATED_STAT_POST_SHIFT - -/* - * Tx Updated Status Main Tap - * - * A value in this register gives the value of the current status transmitted - * to the link partner for the main Tap - * 1 1 = maximum - * 1 0 = minimum - * 0 1 = updated - * 0 0 = not_updated - */ -#define C10GB_LT_TX_UPDATED_STAT_MAIN_OFFSET C10GB_LT_TX_UPDATED_STATUS_REG_OFFSET -#define C10GB_LT_TX_UPDATED_STAT_MAIN_SHIFT (12U) -#define C10GB_LT_TX_UPDATED_STAT_MAIN_MASK BIT_MASK_2_BITS << \ - C10GB_LT_TX_UPDATED_STAT_MAIN_SHIFT - -/* - * Link Training State Pre Tap - * - * A value in this register gives the value of the coefficient update state - * machine for the pre Tap - * IDLE = 3'b000 - * NOT_UPDATED = 3'b001 - * UPDATE_COEFF = 3'b011 - * MAXIMUM = 3'b010 - * UPDATED = 3'b110 - * MINIMUM = 3'b100 - */ -#define C10GB_LT_STATE_PRE_OFFSET C10GB_LT_TX_UPDATED_STATUS_REG_OFFSET -#define C10GB_LT_STATE_PRE_SHIFT (8U) -#define C10GB_LT_STATE_PRE_MASK BIT_MASK_3_BITS << \ - C10GB_LT_STATE_PRE_SHIFT - -/* - * Link Training State Post Tap - * - * A value in this register gives the value of the coefficient update state - * machine for the post Tap - * IDLE = 3'b000 - * NOT_UPDATED = 3'b001 - * UPDATE_COEFF = 3'b011 - * MAXIMUM = 3'b010 - * UPDATED = 3'b110 - * MINIMUM = 3'b100 - */ -#define C10GB_LT_STATE_POST_OFFSET C10GB_LT_TX_UPDATED_STATUS_REG_OFFSET -#define C10GB_LT_STATE_POST_SHIFT (4U) -#define C10GB_LT_STATE_POST_MASK BIT_MASK_3_BITS << \ - C10GB_LT_STATE_POST_SHIFT - -/* - * Link Training State Main Tap - * - * A value in this register gives the value of the coefficient update state - * machine for the main Tap - * IDLE = 3'b000 - * NOT_UPDATED = 3'b001 - * UPDATE_COEFF = 3'b011 - * MAXIMUM = 3'b010 - * UPDATED = 3'b110 - * MINIMUM = 3'b100 - */ -#define C10GB_LT_STATE_MAIN_OFFSET C10GB_LT_TX_UPDATED_STATUS_REG_OFFSET -#define C10GB_LT_STATE_MAIN_SHIFT (0U) -#define C10GB_LT_STATE_MAIN_MASK BIT_MASK_3_BITS << \ - C10GB_LT_STATE_MAIN_SHIFT - -/*------------------------------------------------------------------------------ - * Received Coefficient Status Register - */ -#define C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET (0x16U << 2U) - -/* - * New Coefficient Received - * - * A value in this register gives the value of the new coefficient received - * from the link partner - */ -#define C10GB_LT_NEW_RCVD_COEFF_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET -#define C10GB_LT_NEW_RCVD_COEFF_SHIFT (16U) -#define C10GB_LT_NEW_RCVD_COEFF_MASK BIT_MASK_16_BITS << \ - C10GB_LT_NEW_RCVD_COEFF_SHIFT - -/* - * Preset - * - * 1 = Pre-set coefficients - * 0 = Normal operation - */ -#define C10GB_LT_RCVD_COEFF_PRESET_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET -#define C10GB_LT_RCVD_COEFF_PRESET_SHIFT (29U) -#define C10GB_LT_RCVD_COEFF_PRESET_MASK MASK_BIT_29 - -/* - * Initialize - * - * 1 = Initialize coefficients - * 0 = Normal operation - */ -#define C10GB_LT_RCVD_COEFF_INIT_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET -#define C10GB_LT_RCVD_COEFF_INIT_SHIFT (28U) -#define C10GB_LT_RCVD_COEFF_INIT_MASK MASK_BIT_28 - -/* - * Post tap coefficient update - * - * 1 1 = Reserved - * 0 1 = Increment - * 1 0 = Decrement - * 0 0 = Hold - */ -#define C10GB_LT_RCVD_COEFF_POST_UPDATE_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET -#define C10GB_LT_RCVD_COEFF_POST_UPDATE_SHIFT (20U) -#define C10GB_LT_RCVD_COEFF_POST_UPDATE_MASK BIT_MASK_2_BITS << \ - C10GB_LT_RCVD_COEFF_POST_UPDATE_SHIFT - -/* - * Main tap coefficient update - * - * 1 1 = Reserved - * 0 1 = Increment - * 1 0 = Decrement - * 0 0 = Hold - */ -#define C10GB_LT_RCVD_COEFF_MAIN_UPDATE_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET -#define C10GB_LT_RCVD_COEFF_MAIN_UPDATE_SHIFT (18U) -#define C10GB_LT_RCVD_COEFF_MAIN_UPDATE_MASK BIT_MASK_2_BITS << \ - C10GB_LT_RCVD_COEFF_MAIN_UPDATE_SHIFT - -/* - * Pre tap coefficient update - * - * 1 1 = Reserved - * 0 1 = Increment - * 1 0 = Decrement - * 0 0 = Hold - */ -#define C10GB_LT_RCVD_COEFF_PRE_UPDATE_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET -#define C10GB_LT_RCVD_COEFF_PRE_UPDATE_SHIFT (16U) -#define C10GB_LT_RCVD_COEFF_PRE_UPDATE_MASK BIT_MASK_2_BITS << \ - C10GB_LT_RCVD_COEFF_PRE_UPDATE_SHIFT - -/* - * New Status Received - * - * A value in this register gives the value of the new status received from the - * link partner - */ -#define C10GB_LT_NEW_RCVD_STATUS_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET -#define C10GB_LT_NEW_RCVD_STATUS_SHIFT (0U) -#define C10GB_LT_NEW_RCVD_STATUS_MASK BIT_MASK_16_BITS << \ - C10GB_LT_NEW_RCVD_STATUS_SHIFT - -/* - * Receiver Ready - * - * 1 = The remote receiver has determined that training is completed and is - * prepared to receive data. - * 0 = The remote receiver is requesting that training continue. - */ -#define C10GB_LT_RCVD_COEFF_RCVR_READY_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET -#define C10GB_LT_RCVD_COEFF_RCVR_READY_SHIFT (15U) -#define C10GB_LT_RCVD_COEFF_RCVR_READY_MASK MASK_BIT_15 - -/* - * Post tap coefficient value - * - * 1 1 = Maximum - * 1 0 = Minimum - * 0 1 = updated - * 0 0 = Not Updated - */ -#define C10GB_LT_RCVD_COEFF_POST_VALUE_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET -#define C10GB_LT_RCVD_COEFF_POST_VALUE_SHIFT (4U) -#define C10GB_LT_RCVD_COEFF_POST_VALUE_MASK BIT_MASK_2_BITS << \ - C10GB_LT_RCVD_COEFF_POST_VALUE_SHIFT - -/* - * Main tap coefficient value - * - * 1 1 = Maximum - * 1 0 = Minimum - * 0 1 = updated - * 0 0 = Not Updated - */ -#define C10GB_LT_RCVD_COEFF_MAIN_VALUE_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET -#define C10GB_LT_RCVD_COEFF_MAIN_VALUE_SHIFT (2U) -#define C10GB_LT_RCVD_COEFF_MAIN_VALUE_MASK BIT_MASK_2_BITS << \ - C10GB_LT_RCVD_COEFF_MAIN_VALUE_SHIFT - -/* - * Pre tap coefficient value - * - * 1 1 = Maximum - * 1 0 = Minimum - * 0 1 = updated - * 0 0 = Not Updated - */ -#define C10GB_LT_RCVD_COEFF_PRE_VALUE_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET -#define C10GB_LT_RCVD_COEFF_PRE_VALUE_SHIFT (0U) -#define C10GB_LT_RCVD_COEFF_PRE_VALUE_MASK BIT_MASK_2_BITS << \ - C10GB_LT_RCVD_COEFF_PRE_VALUE_SHIFT - -/*------------------------------------------------------------------------------ - * TX Coefficient Configuration Register - */ -#define C10GB_LT_TX_COEFF_CFG_REG_OFFSET (0x18U << 2U) - -/* - * Hold Pre Cursor Send - * - * If “1” then hold coefficient is sent to the link partner for pre cursor - */ -#define C10GB_LT_TX_HOLD_PRE_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET -#define C10GB_LT_TX_HOLD_PRE_SHIFT (10U) -#define C10GB_LT_TX_HOLD_PRE_MASK MASK_BIT_10 - -/* - * Decrement Pre Cursor Send - * - * If “1” then the decrement coefficient is sent to the link partner for pre - * cursor - */ -#define C10GB_LT_TX_DEC_PRE_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET -#define C10GB_LT_TX_DEC_PRE_SHIFT (9U) -#define C10GB_LT_TX_DEC_PRE_MASK MASK_BIT_9 - -/* - * Increment Pre Cursor Send - * - * If “1” then the increment coefficient is sent to the link partner for pre - * cursor - */ -#define C10GB_LT_TX_INC_PRE_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET -#define C10GB_LT_TX_INC_PRE_SHIFT (8U) -#define C10GB_LT_TX_INC_PRE_MASK MASK_BIT_8 - -/* - * Hold Post Cursor Send - * - * If “1” then the hold coefficient is sent to the link partner for post - * cursor - */ -#define C10GB_LT_TX_HOLD_POST_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET -#define C10GB_LT_TX_HOLD_POST_SHIFT (6U) -#define C10GB_LT_TX_HOLD_POST_MASK MASK_BIT_6 - -/* - * Decrement Post Cursor Send - * - * If “1” then the decrement coefficient is sent to the link partner for post - * cursor - */ -#define C10GB_LT_TX_DEC_POST_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET -#define C10GB_LT_TX_DEC_POST_SHIFT (5U) -#define C10GB_LT_TX_DEC_POST_MASK MASK_BIT_5 - -/* - * Increment Post Cursor Send - * - * If “1” then the increment coefficient is sent to the link partner for post - * cursor - */ -#define C10GB_LT_TX_INC_POST_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET -#define C10GB_LT_TX_INC_POST_SHIFT (4U) -#define C10GB_LT_TX_INC_POST_MASK MASK_BIT_4 - -/* - * Hold Main Cursor Send - * - * If “1” then the hold coefficient is sent to the link partner for mian - * cursor - */ -#define C10GB_LT_TX_HOLD_MAIN_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET -#define C10GB_LT_TX_HOLD_MAIN_SHIFT (2U) -#define C10GB_LT_TX_HOLD_MAIN_MASK MASK_BIT_2 - -/* - * Decrement Main Cursor Send - * - * If “1” then the decrement coefficient is sent to the link partner for main - * cursor - */ -#define C10GB_LT_TX_DEC_MAIN_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET -#define C10GB_LT_TX_DEC_MAIN_SHIFT (1U) -#define C10GB_LT_TX_DEC_MAIN_MASK MASK_BIT_1 - -/* - * Increment Main Cursor Send - * - * If “1” then the increment coefficient is sent to the link partner for main - * cursor - */ -#define C10GB_LT_TX_INC_MAIN_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET -#define C10GB_LT_TX_INC_MAIN_SHIFT (0U) -#define C10GB_LT_TX_INC_MAIN_MASK MASK_BIT_0 - -/*------------------------------------------------------------------------------ - * PRBS error word count register - */ -#define C10GB_LT_PRBS_ERR_WRD_REG_OFFSET (0x1FU << 2U) - -/* - * PRBS error word count - */ -#define C10GB_LT_PRBS_ERR_WRD_CNT_OFFSET C10GB_LT_PRBS_ERR_WRD_REG_OFFSET -#define C10GB_LT_PRBS_ERR_WRD_CNT_SHIFT (0U) -#define C10GB_LT_PRBS_ERR_WRD_CNT_MASK BIT_MASK_32_BITS << \ - C10GB_LT_PRBS_ERR_WRD_CNT_SHIFT - -/*------------------------------------------------------------------------------ - * 10GBASE-KR Status - */ -#define C10GB_LT_STATUS_REG_OFFSET (0x26U << 2U) - -/* - * RX calibration done - * - * 1’ Indicates remote receiver calibration is done. The Firmware should set - * this bit in response to the RX calibration request. - * This Bit will clear the Bit 2 of this Register. - * - */ -#define C10GB_LT_RX_CAL_DONE_OFFSET C10GB_LT_STATUS_REG_OFFSET -#define C10GB_LT_RX_CAL_DONE_SHIFT (6U) -#define C10GB_LT_RX_CAL_DONE_MASK MASK_BIT_6 - -/* - * Request TX equalization - * - * ‘1’ indicates local receiver is responded for remote receiver rx calibration - * request. - * - */ -#define C10GB_LT_REQ_TX_EQUAL_OFFSET C10GB_LT_STATUS_REG_OFFSET -#define C10GB_LT_REQ_TX_EQUAL_SHIFT (5U) -#define C10GB_LT_REQ_TX_EQUAL_MASK MASK_BIT_5 - -/* - * Signal detect - * - * ‘1’ indicated both local and remote receiver ready. - * - */ -#define C10GB_LT_SIGNAL_DETECT_OFFSET C10GB_LT_STATUS_REG_OFFSET -#define C10GB_LT_SIGNAL_DETECT_SHIFT (4U) -#define C10GB_LT_SIGNAL_DETECT_MASK MASK_BIT_4 - -/* - * Training Fail - * - * ‘1’ indicates 500ms of time is expired during link training - * - */ -#define C10GB_LT_TRAINING_FAIL_OFFSET C10GB_LT_STATUS_REG_OFFSET -#define C10GB_LT_TRAINING_FAIL_SHIFT (3U) -#define C10GB_LT_TRAINING_FAIL_MASK MASK_BIT_3 - -/* - * Request RX calibration - * - * ‘1’ Indicates remote receiver is requested for its calibration - * - */ -#define C10GB_LT_REQ_RX_CAL_OFFSET C10GB_LT_STATUS_REG_OFFSET -#define C10GB_LT_REQ_RX_CAL_SHIFT (2U) -#define C10GB_LT_REQ_RX_CAL_MASK MASK_BIT_2 - -/* - * Link training frame lock - * - * ‘1’ indicates link training frame is detected - * - */ -#define C10GB_LT_FRAME_LOCK_OFFSET C10GB_LT_STATUS_REG_OFFSET -#define C10GB_LT_FRAME_LOCK_SHIFT (1U) -#define C10GB_LT_FRAME_LOCK_MASK MASK_BIT_1 - -/* - * Auto-negotiation good link check - * - * ‘1’ indicates Auto negotiation is completed - * - */ -#define C10GB_AN_GOOD_CHECK_OFFSET C10GB_LT_STATUS_REG_OFFSET -#define C10GB_AN_GOOD_CHECK_SHIFT (0U) -#define C10GB_AN_GOOD_CHECK_MASK MASK_BIT_0 - -/******************************************************************************/ -/* Core10GBaseKR PHY Transmit Control */ -/******************************************************************************/ - -/*------------------------------------------------------------------------------ - * Transmit Control Register - */ -#define C10GB_TX_CTRL_REG_OFFSET (0x0U << 2U) - -/* - * PMA Data Select - * - * PMA TX Data Select. Used to select the TX Raw data from the TX Clause Blocks - * to Serdes Interface. - * 2’b00 – PCS Sublayer clause 49 data will be transmitted to the serdes - * interface - * 2’b10 – Auto Negotiation block, PCS sublayer Clause 73 data will be - * transmitted to the serdes interface - * 2’b11 – Link Training block, PCS sublayer Clause 72 data will be transmitted - * to the serdes interface - * 2’b01 – Reserved - - */ -#define C10GB_TX_CTRL_PMA_DATA_OFFSET C10GB_TX_CTRL_REG_OFFSET -#define C10GB_TX_CTRL_PMA_DATA_SHIFT (0U) -#define C10GB_TX_CTRL_PMA_DATA_MASK BIT_MASK_2_BITS << \ - C10GB_TX_CTRL_PMA_DATA_SHIFT - -/* - * XCVR LOS - * - * Loss of sync signal to the XCVR - * 1 - LOS signal is enabled, XCVR will lock to reference - * 0 - LOS signal is disabled, XCVR will lock to data - */ -#define C10GB_TX_CTRL_XCVR_LOS_OFFSET C10GB_TX_CTRL_REG_OFFSET -#define C10GB_TX_CTRL_XCVR_LOS_SHIFT (4U) -#define C10GB_TX_CTRL_XCVR_LOS_MASK MASK_BIT_4 - -/* - * PCS Tx Reset - * - * Soft reset bit for PCS reset - * 1 - TX logic is reset - * 0 - TX logic is not reset - * Self clearing - */ -#define C10GB_TX_CTRL_TX_RESET_OFFSET C10GB_TX_CTRL_REG_OFFSET -#define C10GB_TX_CTRL_TX_RESET_SHIFT (5U) -#define C10GB_TX_CTRL_TX_RESET_MASK MASK_BIT_5 - -/* - * PCS Rx Reset - * - * Soft reset bit for PCS reset - * 1 - RX logic is reset - * 0 - RX logic is not reset - * Self clearing - */ -#define C10GB_TX_CTRL_RX_RESET_OFFSET C10GB_TX_CTRL_REG_OFFSET -#define C10GB_TX_CTRL_RX_RESET_SHIFT (6U) -#define C10GB_TX_CTRL_RX_RESET_MASK MASK_BIT_6 - -/*------------------------------------------------------------------------------ - * IP version register - */ -#define C10GB_IP_VERSION_REG_OFFSET (0x1U << 2U) - -#define C10GB_IP_VERSION_OFFSET C10GB_IP_VERSION_REG_OFFSET -#define C10GB_IP_VERSION_SHIFT (0U) -#define C10GB_IP_VERSION_MASK BIT_MASK_32_BITS << \ - C10GB_IP_VERSION_SHIFT - - -/******************************************************************************/ -/* Core10GBaseKR PHY Receive Status */ -/******************************************************************************/ - -/*------------------------------------------------------------------------------ - * Receive Status Register - */ -#define C10GB_RX_STATUS_REG_OFFSET (0x0U << 2U) - -/* - * PCS49 Status - * - * Receive Status signal - * 1 – Receiver has attained Block Lock - * 0 – Receiver has not attained the Block Lock - */ -#define C10GB_RX_STATUS_PCS49_OFFSET C10GB_RX_STATUS_REG_OFFSET -#define C10GB_RX_STATUS_PCS49_SHIFT (0U) -#define C10GB_RX_STATUS_PCS49_MASK BIT_MASK_2_BITS << \ - C10GB_RX_STATUS_PCS49_SHIFT - -/******************************************************************************/ -/* Core10GBaseKR_PHY Memory Map */ -/******************************************************************************/ - #define C10GB_AN_BASE_OFFSET (0x0U << 8U) - #define C10GB_LT_BASE_OFFSET (0x4U << 8U) - #define C10GB_TX_CTRL_BASE_OFFSET (0x8U << 8U) - #define C10GB_RX_STATUS_BASE_OFFSET (0x9U << 8U) - -/// @endcond - -#ifdef __cplusplus -} -#endif - -#endif /* CORE10GBASEKR_PHY_REG_H_ */ +/** + * Copyright 2022 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * @file core10gbasekr_phy_reg.h + * @author Microchip FPGA Embedded Systems Solutions + * @brief Core10GBaseKR PHY memory map + * + */ + +#ifndef CORE10GBASEKR_PHY_REG_H_ +#define CORE10GBASEKR_PHY_REG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/// @cond @private + +#include "uint_32_bit_masks.h" + +#define __I const volatile +#define __O volatile +#define __IO volatile + +/******************************************************************************/ +/* Core10GBaseKR PHY Clause 73 (Auto-negotiation) */ +/******************************************************************************/ + +/** + * AN_CONTROL register details + */ +#define C10GB_AN_CONTROL_REG_OFFSET (0x0U << 2U) + +/** + * Auto-negotiation Restart + * + * Restart_negotiation. Self clears, and always reads as 0. + */ +#define C10GB_AN_RESTART_OFFSET C10GB_AN_CONTROL_REG_OFFSET +#define C10GB_AN_RESTART_MASK MASK_BIT_9 +#define C10GB_AN_RESTART_SHIFT (9U) + +/** + * Auto-negotiation Enable + * + * Auto-negotiation Enable. Writing “1” in this register enables + * auto-negotiation + */ +#define C10GB_AN_ENABLE_OFFSET C10GB_AN_CONTROL_REG_OFFSET +#define C10GB_AN_ENABLE_MASK MASK_BIT_12 +#define C10GB_AN_ENABLE_SHIFT (12U) + +/** + * Auto-negotiation Reset + * + * Main_reset. Self clears. When reads as 0 the reset is complete. + */ +#define C10GB_AN_RESET_OFFSET C10GB_AN_CONTROL_REG_OFFSET +#define C10GB_AN_RESET_MASK MASK_BIT_15 +#define C10GB_AN_RESET_SHIFT (15U) + +/** + * AN_STATUS register details + */ +#define C10GB_AN_STATUS_REG_OFFSET (0x1U << 2U) + +/** + * Auto-negotiation Able + * + * If “1” indicates that Link Partner is Auto-negotiation Able + */ +#define C10GB_AN_CAPABLE_OFFSET C10GB_AN_STATUS_REG_OFFSET +#define C10GB_AN_CAPABLE_MASK MASK_BIT_0 +#define C10GB_AN_CAPABLE_SHIFT (0U) + +/** + * Auto-negotiation Support + * + * If “1” indicates that Auto-negotiation is supported + */ +#define C10GB_AN_SUPPORT_OFFSET C10GB_AN_STATUS_REG_OFFSET +#define C10GB_AN_SUPPORT_MASK MASK_BIT_3 +#define C10GB_AN_SUPPORT_SHIFT (3U) + +/** + * Auto-negotiation Complete + * + * If “1” indicates that AN is complete + */ +#define C10GB_AN_COMPLETE_OFFSET C10GB_AN_STATUS_REG_OFFSET +#define C10GB_AN_COMPLETE_MASK MASK_BIT_5 +#define C10GB_AN_COMPLETE_SHIFT (5U) + +/** + * Auto-negotiation Page Received + * + * Page_RX. If “1” that Page is received from the link partner. Clear on read + */ +#define C10GB_AN_PAGE_RX_OFFSET C10GB_AN_STATUS_REG_OFFSET +#define C10GB_AN_PAGE_RX_MASK MASK_BIT_6 +#define C10GB_AN_PAGE_RX_SHIFT (6U) + +/** + * Auto-negotiation Parallel Fault Detected + * + * Parallel_Detect_fault. Clear on read + */ +#define C10GB_AN_PARALLEL_DETECT_OFFSET C10GB_AN_STATUS_REG_OFFSET +#define C10GB_AN_PARALLEL_DETECT_MASK MASK_BIT_9 +#define C10GB_AN_PARALLEL_DETECT_SHIFT (9U) + +/** + * Auto-negotiation State Variable + * + * This register returns the state variables of the Auto-Negotiation. + * ST_AUTO_NEG_ENABLE = 0x0; + * ST_TRANSMIT_DISABLE = 0x1; + * ST_CAPABILITY_DETECT = 0x2; + * ST_ACKNOWLEDGE_DETECT = 0x3; + * ST_COMPLETE_ACKNOWLE = 0x4; + * ST_AN_GOOD_CHECK = 0x5; + * ST_AN_GOOD = 0x6; + * ST_NEXT_PAGE_WAIT = 0x7; + * ST_NEXT_PAGE_WAIT_TX_IDLE = 0x8; + * ST_LINK_STATUS_CHECK = 0x9; + * ST_PARALLEL_DETECTION_FAULT = 0xA; + */ +#define C10GB_AN_STATE_OFFSET C10GB_AN_STATUS_REG_OFFSET +#define C10GB_AN_STATE_SHIFT (12U) +#define C10GB_AN_STATE_MASK BIT_MASK_4_BITS << C10GB_AN_STATE_SHIFT + +/** + * MR_ADV_CAPABILITY_1 Bits [16:1] + * + * This register gives the value of the bits 16:1 of the Advertisement Ability + * Register + * Bits [4:0] - Selector Field (S[4:0]) is a five-bit wide field, encoding 32 + * possible messages. Selector Field encoding definitions are shown in Annex + * 28A of the IEEE 802.3 specification + * Bits[9:5] -Echoed Nonce Field (E[4:0]) is a 5-bit wide field containing + * the nonce received from the link partner + * Bits[12:10] - Pause Encoding as defined in Annexure 28B of the IEEE 802.3 + * specification + * Bit 13 - Remote Fault (RF) of the base link codeword. The default value is + * logical zero + * Bit 14 -Acknowledge (Ack) is used by the Auto-Negotiation function to + * indicate that a device has successfully received its link partner’s link + * codeword. + * Bit 15 -Next Page (NP) bit. Support of Next Pages is mandatory. If the + * device does not have any Next Pages to send, the NP bit shall be set to + * logical zero + */ +#define C10GB_AN_MR_ADV_CAPABILITY_1_REG_OFFSET (0x10U << 2U) + +/** + * MR_ADV_CAPABILITY_2 Bits [32:17] + * + * This register gives the value of the bits 32:17 of the Advertisement Ability + * Register + * Bits[20:16] – Transmitted Nonce Field + * Bits[31:21] – Technology Ability Field bits[ 10:0] . Technology Ability + * Field is a 25-bit wide field containing information indicating supported + * technologies specific to the selector field value when used with the + * Auto-Negotiation for Backplane Ethernet. + */ +#define C10GB_AN_MR_ADV_CAPABILITY_2_REG_OFFSET (0x11U << 2U) + +/** + * MR_ADV_CAPABILITY_3 Bits [48:33] + * + * This register gives the value of the bits 48:33 of the Advertisement Ability + * Register + * Bits [45:32] – Technology Ability Field bits[ 25:11]. For Technology Ability + * Field encoding refer to Table 73-4 of the IEEE specification + * Bits [47:46] - FEC Capability (FEC Not supported in current implementation). + * Bits [47:46] - FEC Capability (FEC Not supported in current implementation). + * Bit 46 - FEC ability, if set to ‘1’ PHY has FEC Ability + * Bit 47 - FEC requested When the FEC requested bit is set to logical one, it + * indicates a request to enable FEC on the link. + */ +#define C10GB_AN_MR_ADV_CAPABILITY_3_REG_OFFSET (0x12U << 2U) + +/** + * Adevertisment Ability Registers Details + */ +#define C10GB_AN_ADV_CAPABILITY_SHIFT (0U) +#define C10GB_AN_ADV_CAPABILITY_MASK BIT_MASK_16_BITS << C10GB_AN_ADV_CAPABILITY_SHIFT + +/** + * MR_LP_BASE_PAGE_CAPABILITY_1 Bits [16:1] + * + * This register gives the value of the bits 16:1 of the Link Partner Base Page + * Ability Register. The bits definition are same as Advertisement ability + * register -1 + */ +#define C10GB_AN_MR_LP_BASE_PG_CAPABILITY_1_REG_OFFSET (0x13U << 2U) + +/** + * MR_LP_BASE_PAGE_CAPABILITY_2 Bits [32:17] + * + * This register gives the value of the bits 32:17 of the Link Partner Base Page + * Ability Register. The bits definition are same as Advertisement ability + * register -2 + */ +#define C10GB_AN_MR_LP_BASE_PG_CAPABILITY_2_REG_OFFSET (0x14U << 2U) + +/** + * MR_LP_BASE_PAGE_CAPABILITY_3 Bits [48:33] + * + * This register gives the value of the bits 48:33 of the Link Partner Base Page + * Ability Register. The bits definition are same as Advertisement ability + * register -3 + * + */ +#define C10GB_AN_MR_LP_BASE_PG_CAPABILITY_3_REG_OFFSET (0x15U << 2U) + +/** + * Link Partner Base Page Ability Registers Details + */ +#define C10GB_AN_LP_BASE_PAGE_CAPABILITY_SHIFT (0U) +#define C10GB_AN_LP_BASE_PAGE_CAPABILITY_MASK \ + BIT_MASK_16_BITS << C10GB_AN_LP_BASE_PAGE_CAPABILITY_SHIFT + +/** + * MR_XNP_TRANSMIT_1 Bits [16:1] + * + * This register gives the value of the bits 16:1 of the XNP(next page)Transmit + * Register. + * Bit[10:0] – Message Code Field (M[10:0]) is an eleven bit wide field, + * encoding 2048 possible messages. Message Code Field definitions are shown in + * Annex 28C of the IEEE 802.3 specification + * Bit 11 – Toggle (T) is used by the Arbitration function to ensure + * synchronization with the Link Partner during Next Page exchange. This bit + * shall always take the opposite value of the Toggle bit in the previously + * exchanged link codeword + * Bit 12 – Acknowledge 2 (Ack2) is used by the Next Page function to indicate + * that a device has the ability to comply with the message. Ack2 shall be set + * as follows: + * 0 - cannot comply with message + * 1 - will comply with message + * Bit 13 – Message Page bit + * 0 – Unformatted Page + * 1 – Message Page + * Bit 14 – Acknowledge. Acknowledge (Ack) is used by the Auto-Negotiation + * function to indicate that a device has successfully received its Link + * Partner’s link codeword + * Bit 15 - Next Page Bit + * 0 - last page + * 1 - additional Next Page(s) will follow + */ +#define C10GB_AN_MR_XNP_TRANSMIT_1_REG_OFFSET (0x16U << 2U) + +/** + * MR_XNP_TRANSMIT_2 Bits [32:17] + * + * This register gives the value of the bits 32:17 of the XNP Transmit Register. + * This value corresponds to the Bits[31:16] of the Unformatted Code Field of + * the Next Page Register. + */ +#define C10GB_AN_MR_XNP_TRANSMIT_2_REG_OFFSET (0x17U << 2U) + +/** + * MR_XNP_TRANSMIT_3 Bits [48:33] + * + * This register gives the value of the bits 48:33 of the XNP Transmit Register. + * This value corresponds to the Bits[47:32] of the Unformatted Code Field of + * the Next Page Register. + */ +#define C10GB_AN_MR_XNP_TRANSMIT_3_REG_OFFSET (0x18U << 2U) + +/** + * XNP Transmit Registers Details + */ +#define C10GB_AN_XNP_TRANSMIT_SHIFT (0U) +#define C10GB_AN_XNP_TRANSMIT_MASK BIT_MASK_16_BITS << C10GB_AN_XNP_TRANSMIT_SHIFT + +/** + * LP_XNP_CAPABILITY_1 Bits [16:1] + * + * This register gives the value of the bits 16:1 of the Link Partner next page + * Ability register. The bits definition are same as XNP Transmit register -1 + */ +#define C10GB_AN_LP_XNP_CAPABILITY_1_REG_OFFSET (0x19U << 2U) + +/** + * LP_XNP_CAPABILITY_2 Bits [32:17] + * + * This register gives the value of the bits 32:17 of the Link Partner next page + * Ability register. The bits definition are same as XNP Transmit register -2 + */ +#define C10GB_AN_LP_XNP_CAPABILITY_2_REG_OFFSET (0x1aU << 2U) + +/** + * LP_XNP_CAPABILITY_3 Bits [48:33] + * + * This register gives the value of the bits 48:33 of the Link Partner next page + * Ability register. The bits definition are same as XNP Transmit register -3 + */ +#define C10GB_AN_LP_XNP_CAPABILITY_3_REG_OFFSET (0x1bU << 2U) + +/** + * Link Partner Next Page Ability Registers Details + */ +#define C10GB_AN_LP_XNP_CAPABILITY_SHIFT (0U) +#define C10GB_AN_LP_XNP_CAPABILITY_MASK BIT_MASK_16_BITS << C10GB_AN_LP_XNP_CAPABILITY_SHIFT + +/** + * AN Link Fail Inhibit Timer + * + * An_link_fail_inhibit_timer is 500ms timer which starts incrementing in + * AN GOOD CHECK state (This state is indication of AN completion) and if it + * elapses in during this state then the Auto-negotiation process starts again + */ +#define C10GB_AN_LINK_FAIL_INHIBIT_TIMER_REG_OFFSET (0x0dU << 2U) + +/******************************************************************************/ +/* Core10GBaseKR PHY Clause 72 (Link Training) */ +/******************************************************************************/ + +/** + * Link Training Control Register + */ +#define C10GB_LT_CTRL_REG_OFFSET (0x0U << 2U) + +/** + * Link Training Initialize + * + * If “1” initialize coefficient is transmitted to the link partner + */ +#define C10GB_LT_INIT_OFFSET C10GB_LT_CTRL_REG_OFFSET +#define C10GB_LT_INIT_SHIFT (3U) +#define C10GB_LT_INIT_MASK MASK_BIT_3 + +/** + * Link Training Preset + * + * If “1” preset coefficient is transmitted to the link partner + */ +#define C10GB_LT_PRESET_OFFSET C10GB_LT_CTRL_REG_OFFSET +#define C10GB_LT_PRESET_SHIFT (2U) +#define C10GB_LT_PRESET_MASK MASK_BIT_2 + +/** + * Link Restart Training + * + * A write of “1” to this field brings the link training IP in reset mode. + * To bring the Link training IP out of reset, write a value of 0x0 into this + * register + */ +#define C10GB_LT_RESTART_TRAINING_OFFSET C10GB_LT_CTRL_REG_OFFSET +#define C10GB_LT_RESTART_TRAINING_SHIFT (1U) +#define C10GB_LT_RESTART_TRAINING_MASK MASK_BIT_1 + +/** + * Link Training Enable + * + * If “1” enables the link training. This bit should be enabled from the + * software after the AN_GOOD_CHK interrupt is received by the Firmware + */ +#define C10GB_LT_RESTART_EN_OFFSET C10GB_LT_CTRL_REG_OFFSET +#define C10GB_LT_RESTART_EN_SHIFT (0U) +#define C10GB_LT_RESTART_EN_MASK MASK_BIT_0 + +/** + * Max Wait Timer Configuration + * + * The value in the MAX wait timer should be configured to 500ms, the training + * state diagram enters into the training failure state once the timer reaches + * 500ms. + */ +#define C10GB_LT_MAX_WAIT_TIMER_REG_OFFSET (0x1U << 2U) + +#define C10GB_LT_MAX_WAIT_TIMER_OFFSET C10GB_LT_MAX_WAIT_TIMER_REG_OFFSET +#define C10GB_LT_MAX_WAIT_TIMER_SHIFT (0U) +#define C10GB_LT_MAX_WAIT_TIMER_MASK BIT_MASK_32_BITS << C10GB_LT_MAX_WAIT_TIMER_SHIFT + +/** + * Frame WAIT Timer Configuration Register + * + * The value in the frame WAIT Timer register should be between 100 to 300 + * frames. The default value is configured to 100 frames. + */ +#define C10GB_LT_FRM_WAIT_TIMER_REG_OFFSET (0x2U << 2U) + +#define C10GB_LT_FRM_WAIT_TIMER_OFFSET C10GB_LT_FRM_WAIT_TIMER_REG_OFFSET +#define C10GB_LT_FRM_WAIT_TIMER_SHIFT (0U) +#define C10GB_LT_FRM_WAIT_TIMER_MASK BIT_MASK_32_BITS << C10GB_LT_FRM_WAIT_TIMER_SHIFT + +/** + * Preset MAIN-TAP Configuration Register + * + * The value in this register gives the main TAP value, when the preset + * Coefficient is received from the Link Partner. The Link Training Algorithm + * starts from this TAP value. + */ +#define C10GB_LT_PRESET_MAIN_TAP_REG_OFFSET (0x3U << 2U) + +#define C10GB_LT_PRESET_MAIN_TAP_OFFSET C10GB_LT_PRESET_MAIN_TAP_REG_OFFSET +#define C10GB_LT_PRESET_MAIN_TAP_SHIFT (0U) +#define C10GB_LT_PRESET_MAIN_TAP_MASK BIT_MASK_16_BITS << C10GB_LT_PRESET_MAIN_TAP_SHIFT + +/** + * Preset Post-TAP Configuration Register + * + * The value in this register gives the post-TAP value when the preset + * Coefficient is received from the Link Partner. The Link Training Algorithm + * starts from this TAP value. + */ +#define C10GB_LT_PRESET_POST_TAP_REG_OFFSET (0x4U << 2U) + +#define C10GB_LT_PRESET_POST_TAP_OFFSET C10GB_LT_PRESET_POST_TAP_REG_OFFSET +#define C10GB_LT_PRESET_POST_TAP_SHIFT (0U) +#define C10GB_LT_PRESET_POST_TAP_MASK BIT_MASK_16_BITS << C10GB_LT_PRESET_POST_TAP_SHIFT + +/** + * Preset Pre-TAP Configuration Register + * + * The value in this register gives the pre-TAP when the preset Coefficient is + * received from the Link Partner. The Link Training Algorithm starts from this + * TAP value. + */ +#define C10GB_LT_PRESET_PRE_TAP_REG_OFFSET (0x5U << 2U) + +#define C10GB_LT_PRESET_PRE_TAP_OFFSET C10GB_LT_PRESET_PRE_TAP_REG_OFFSET +#define C10GB_LT_PRESET_PRE_TAP_SHIFT (0U) +#define C10GB_LT_PRESET_PRE_TAP_MASK BIT_MASK_16_BITS << C10GB_LT_PRESET_PRE_TAP_SHIFT + +/** + * Initialize MAIN-TAP Configuration Register + * + * The value in this register gives the main TAP value, when the Initialize + * Coefficient is received from the Link Partner. + */ +#define C10GB_LT_INIT_MAIN_TAP_REG_OFFSET (0x6U << 2U) + +#define C10GB_LT_INIT_MAIN_TAP_OFFSET C10GB_LT_INIT_MAIN_TAP_REG_OFFSET +#define C10GB_LT_INIT_MAIN_TAP_SHIFT (0U) +#define C10GB_LT_INIT_MAIN_TAP_MASK BIT_MASK_16_BITS << C10GB_LT_INIT_MAIN_TAP_SHIFT + +/** + * Initialize Post-TAP Configuration Register + * + * The value in this register gives the post-TAP value when the Initialize + * Coefficient is received from the Link Partner. + */ +#define C10GB_LT_INIT_POST_TAP_REG_OFFSET (0x7U << 2U) + +#define C10GB_LT_INIT_POST_TAP_OFFSET C10GB_LT_INIT_POST_TAP_REG_OFFSET +#define C10GB_LT_INIT_POST_TAP_SHIFT (0U) +#define C10GB_LT_INIT_POST_TAP_MASK BIT_MASK_16_BITS << C10GB_LT_INIT_POST_TAP_SHIFT + +/** + * Initialize Pre-TAP Configuration Register + * + * The value in this register gives the pre-TAP when the Initialize Coefficient + * is received from the Link Partner. + */ +#define C10GB_LT_INIT_PRE_TAP_REG_OFFSET (0x8U << 2U) + +#define C10GB_LT_INIT_PRE_TAP_OFFSET C10GB_LT_INIT_PRE_TAP_REG_OFFSET +#define C10GB_LT_INIT_PRE_TAP_SHIFT (0U) +#define C10GB_LT_INIT_PRE_TAP_MASK BIT_MASK_16_BITS << C10GB_LT_INIT_PRE_TAP_SHIFT + +/** + * Maximum Coefficient Limit of Main Tap Configuration Register + * + * The value in this register gives the Maximum value of the main TAP setting + * which will be tested for the TX equalization for the optimum main tap + * settings. + */ +#define C10GB_LT_MAX_MAIN_TAP_REG_OFFSET (0x9U << 2U) + +#define C10GB_LT_MAX_MAIN_TAP_OFFSET C10GB_LT_MAX_MAIN_TAP_REG_OFFSET +#define C10GB_LT_MAX_MAIN_TAP_SHIFT (0U) +#define C10GB_LT_MAX_MAIN_TAP_MASK BIT_MASK_16_BITS << C10GB_LT_MAX_MAIN_TAP_SHIFT + +/** + * Minimum Coefficient Limit of Main Tap Configuration Register + * + * The value in this register gives the minimum value of the main TAP setting + * which will be tested for the TX equalization for the optimum main tap + * settings. + */ +#define C10GB_LT_MIN_MAIN_TAP_REG_OFFSET (0xAU << 2U) + +#define C10GB_LT_MIN_MAIN_TAP_OFFSET C10GB_LT_MIN_MAIN_TAP_REG_OFFSET +#define C10GB_LT_MIN_MAIN_TAP_SHIFT (0U) +#define C10GB_LT_MIN_MAIN_TAP_MASK BIT_MASK_16_BITS << C10GB_LT_MIN_MAIN_TAP_SHIFT + +/** + * Maximum Coefficient Limit of Post Tap Configuration Register + * + * The value in this register gives the Maximum value of the post TAP setting + * which will be tested for the TX equalization for the optimum post tap + * settings. + */ +#define C10GB_LT_MAX_POST_TAP_REG_OFFSET (0xBU << 2U) + +#define C10GB_LT_MAX_POST_TAP_OFFSET C10GB_LT_MAX_POST_TAP_REG_OFFSET +#define C10GB_LT_MAX_POST_TAP_SHIFT (0U) +#define C10GB_LT_MAX_POST_TAP_MASK BIT_MASK_16_BITS << C10GB_LT_MAX_POST_TAP_SHIFT + +/** + * Minimum Coefficient Limit of Post Tap Configuration Register + * + * The value in this register gives the minimum value of the post TAP setting + * which will be tested for the TX equalization for the optimum post tap + * settings. + */ +#define C10GB_LT_MIN_POST_TAP_REG_OFFSET (0xCU << 2U) + +#define C10GB_LT_MIN_POST_TAP_OFFSET C10GB_LT_MIN_POST_TAP_REG_OFFSET +#define C10GB_LT_MIN_POST_TAP_SHIFT (0U) +#define C10GB_LT_MIN_POST_TAP_MASK BIT_MASK_16_BITS << C10GB_LT_MIN_POST_TAP_SHIFT + +/** + * Maximum Coefficient Limit of Pre Tap Configuration Register + * + * The value in this register gives the Maximum value of the pre TAP setting + * which will be tested for the TX equalization for the optimum pre tap + * settings. + */ +#define C10GB_LT_MAX_PRE_TAP_REG_OFFSET (0xDU << 2U) + +#define C10GB_LT_MAX_PRE_TAP_OFFSET C10GB_LT_MAX_PRE_TAP_REG_OFFSET +#define C10GB_LT_MAX_PRE_TAP_SHIFT (0U) +#define C10GB_LT_MAX_PRE_TAP_MASK BIT_MASK_16_BITS << C10GB_LT_MAX_PRE_TAP_SHIFT + +/** + * Minimum Coefficient Limit of Pre Tap Configuration Register + * + * The value in this register gives the minimum value of the pre TAP setting + * which will be tested for the TX equalization for the optimum pre tap + * settings. + */ +#define C10GB_LT_MIN_PRE_TAP_REG_OFFSET (0xEU << 2U) + +#define C10GB_LT_MIN_PRE_TAP_OFFSET C10GB_LT_MIN_PRE_TAP_REG_OFFSET +#define C10GB_LT_MIN_PRE_TAP_SHIFT (0U) +#define C10GB_LT_MIN_PRE_TAP_MASK BIT_MASK_16_BITS << C10GB_LT_MIN_PRE_TAP_SHIFT + +/** + * TX Equalization Register + */ +#define C10GB_LT_TX_EQUAL_REG_OFFSET (0xFU << 2U) + +/** + * TX Equalization Pre Tap Done + * + * A write to “1” in this field indicates that that tx_equalization is done for + * the PRE TAP + */ +#define C10GB_LT_TX_EQUAL_PRE_DONE_OFFSET C10GB_LT_TX_EQUAL_REG_OFFSET +#define C10GB_LT_TX_EQUAL_PRE_DONE_SHIFT (3U) +#define C10GB_LT_TX_EQUAL_PRE_DONE_MASK MASK_BIT_3 + +/** + * TX Equalization Post Tap Done + * + * A write to “1” in this field indicates that that tx_equalization is done for + * the post TAP + */ +#define C10GB_LT_TX_EQUAL_POST_DONE_OFFSET C10GB_LT_TX_EQUAL_REG_OFFSET +#define C10GB_LT_TX_EQUAL_POST_DONE_SHIFT (2U) +#define C10GB_LT_TX_EQUAL_POST_DONE_MASK MASK_BIT_2 + +/** + * TX Equalization Main Tap Done + * + * A write to “1” in this field indicates that that tx_equalization is done for + * the main TAP + */ +#define C10GB_LT_TX_EQUAL_MAIN_DONE_OFFSET C10GB_LT_TX_EQUAL_REG_OFFSET +#define C10GB_LT_TX_EQUAL_MAIN_DONE_SHIFT (1U) +#define C10GB_LT_TX_EQUAL_MAIN_DONE_MASK MASK_BIT_1 + +/** + * TX Equalization Done + * + * A write to “1” in this field indicates that that tx_equalization is done for + * all the TAPs (pre, post and main) + */ +#define C10GB_LT_TX_EQUAL_DONE_OFFSET C10GB_LT_TX_EQUAL_REG_OFFSET +#define C10GB_LT_TX_EQUAL_DONE_SHIFT (0U) +#define C10GB_LT_TX_EQUAL_DONE_MASK MASK_BIT_0 + +/** + * Local Receiver Lock Register + */ +#define C10GB_LT_LOCAL_RCVR_LOCK_REG_OFFSET (0x10U << 2U) + +/** + * Local Receiver Locked + * + * Write “1” to this register from the software once the local receiver is + * ready + */ +#define C10GB_LT_LOCAL_RCVR_LOCKED_OFFSET C10GB_LT_LOCAL_RCVR_LOCK_REG_OFFSET +#define C10GB_LT_LOCAL_RCVR_LOCKED_SHIFT (0U) +#define C10GB_LT_LOCAL_RCVR_LOCKED_MASK MASK_BIT_0 + +/** + * TX New Main Tap Register + */ +#define C10GB_LT_TX_NEW_MAIN_TAP_REG_OFFSET (0x11U << 2U) + +/** + * TX New Main Tap + * + * A value in this register gives the value of the new main tap value, which + * is used to update the TX equalization SerDes registers. + */ +#define C10GB_LT_TX_NEW_MAIN_TAP_OFFSET C10GB_LT_TX_NEW_MAIN_TAP_REG_OFFSET +#define C10GB_LT_TX_NEW_MAIN_TAP_SHIFT (0U) +#define C10GB_LT_TX_NEW_MAIN_TAP_MASK BIT_MASK_8_BITS << C10GB_LT_TX_NEW_MAIN_TAP_SHIFT + +/** + * TX New Post Tap Register + */ +#define C10GB_LT_TX_NEW_POST_TAP_REG_OFFSET (0x12U << 2U) + +/** + * TX New Post Tap + * + * A value in this register gives the value of the new Post tap value, which + * is used to update the TX equalization SerDes registers. + */ +#define C10GB_LT_TX_NEW_POST_TAP_OFFSET C10GB_LT_TX_NEW_POST_TAP_REG_OFFSET +#define C10GB_LT_TX_NEW_POST_TAP_SHIFT (0U) +#define C10GB_LT_TX_NEW_POST_TAP_MASK BIT_MASK_8_BITS << C10GB_LT_TX_NEW_POST_TAP_SHIFT + +/** + * TX New Pre Tap Register + */ +#define C10GB_LT_TX_NEW_PRE_TAP_REG_OFFSET (0x13U << 2U) + +/** + * TX New Pre Tap + * + * A value in this register gives the value of the new Pre tap value, which is + * used to update the TX equalization SerDes registers. + */ +#define C10GB_LT_TX_NEW_PRE_TAP_OFFSET C10GB_LT_TX_NEW_PRE_TAP_REG_OFFSET +#define C10GB_LT_TX_NEW_PRE_TAP_SHIFT (0U) +#define C10GB_LT_TX_NEW_PRE_TAP_MASK BIT_MASK_8_BITS << C10GB_LT_TX_NEW_PRE_TAP_SHIFT + +/** + * Training State Machine Status + */ +#define C10GB_LT_TRAINING_SM_STATUS_REG_OFFSET (0x14U << 2U) + +/** + * Remote Receiver Ready + * + * If “1” it indicates that remote receiver is ready + */ +#define C10GB_LT_REMOTE_TRAINED_OFFSET C10GB_LT_TRAINING_SM_STATUS_REG_OFFSET +#define C10GB_LT_REMOTE_TRAINED_SHIFT (4U) +#define C10GB_LT_REMOTE_TRAINED_MASK MASK_BIT_4 + +/** + * Link Up + * + * If “1” it indicates that Link is ready + */ +#define C10GB_LT_LINK_UP_OFFSET C10GB_LT_TRAINING_SM_STATUS_REG_OFFSET +#define C10GB_LT_LINK_UP_SHIFT (3U) +#define C10GB_LT_LINK_UP_MASK MASK_BIT_3 + +/** + * Training State Machine + * + * The value in this register gives the current values of the training state + * machine. + * IDLE = 3'b000 + * INITIALIZE = 3'b001 + * SEND_TRAINING = 3'b011 + * TRAIN_LOCAL = 3'b010 + * TRAIN_REMOTE = 3'b110 + * LINK_READY = 3'b111 + * SEND_DATA = 3'b101 + * RAINING_FAILURE = 3'b100 + + */ +#define C10GB_LT_TRAINING_SM_OFFSET C10GB_LT_TRAINING_SM_STATUS_REG_OFFSET +#define C10GB_LT_TRAINING_SM_SHIFT (0U) +#define C10GB_LT_TRAINING_SM_MASK BIT_MASK_2_BITS << C10GB_LT_TRAINING_SM_SHIFT + +/** + * TX Updated Status Register + */ +#define C10GB_LT_TX_UPDATED_STATUS_REG_OFFSET (0x15U << 2U) + +/** + * Tx Updated Status Pre Tap + * + * A value in this register gives the value of the current status transmitted + * to the link partner for the pre Tap + * 1 1 = maximum + * 1 0 = minimum + * 0 1 = updated + * 0 0 = not_updated + */ +#define C10GB_LT_TX_UPDATED_STAT_PRE_OFFSET C10GB_LT_TX_UPDATED_STATUS_REG_OFFSET +#define C10GB_LT_TX_UPDATED_STAT_PRE_SHIFT (16U) +#define C10GB_LT_TX_UPDATED_STAT_PRE_MASK BIT_MASK_2_BITS << C10GB_LT_TX_UPDATED_STAT_PRE_SHIFT + +/** + * Tx Updated Status Post Tap + * + * A value in this register gives the value of the current status transmitted + * to the link partner for the post Tap + * 1 1 = maximum + * 1 0 = minimum + * 0 1 = updated + * 0 0 = not_updated + */ +#define C10GB_LT_TX_UPDATED_STAT_POST_OFFSET C10GB_LT_TX_UPDATED_STATUS_REG_OFFSET +#define C10GB_LT_TX_UPDATED_STAT_POST_SHIFT (14U) +#define C10GB_LT_TX_UPDATED_STAT_POST_MASK BIT_MASK_2_BITS << C10GB_LT_TX_UPDATED_STAT_POST_SHIFT + +/** + * Tx Updated Status Main Tap + * + * A value in this register gives the value of the current status transmitted + * to the link partner for the main Tap + * 1 1 = maximum + * 1 0 = minimum + * 0 1 = updated + * 0 0 = not_updated + */ +#define C10GB_LT_TX_UPDATED_STAT_MAIN_OFFSET C10GB_LT_TX_UPDATED_STATUS_REG_OFFSET +#define C10GB_LT_TX_UPDATED_STAT_MAIN_SHIFT (12U) +#define C10GB_LT_TX_UPDATED_STAT_MAIN_MASK BIT_MASK_2_BITS << C10GB_LT_TX_UPDATED_STAT_MAIN_SHIFT + +/** + * Link Training State Pre Tap + * + * A value in this register gives the value of the coefficient update state + * machine for the pre Tap + * IDLE = 3'b000 + * NOT_UPDATED = 3'b001 + * UPDATE_COEFF = 3'b011 + * MAXIMUM = 3'b010 + * UPDATED = 3'b110 + * MINIMUM = 3'b100 + */ +#define C10GB_LT_STATE_PRE_OFFSET C10GB_LT_TX_UPDATED_STATUS_REG_OFFSET +#define C10GB_LT_STATE_PRE_SHIFT (8U) +#define C10GB_LT_STATE_PRE_MASK BIT_MASK_3_BITS << C10GB_LT_STATE_PRE_SHIFT + +/** + * Link Training State Post Tap + * + * A value in this register gives the value of the coefficient update state + * machine for the post Tap + * IDLE = 3'b000 + * NOT_UPDATED = 3'b001 + * UPDATE_COEFF = 3'b011 + * MAXIMUM = 3'b010 + * UPDATED = 3'b110 + * MINIMUM = 3'b100 + */ +#define C10GB_LT_STATE_POST_OFFSET C10GB_LT_TX_UPDATED_STATUS_REG_OFFSET +#define C10GB_LT_STATE_POST_SHIFT (4U) +#define C10GB_LT_STATE_POST_MASK BIT_MASK_3_BITS << C10GB_LT_STATE_POST_SHIFT + +/** + * Link Training State Main Tap + * + * A value in this register gives the value of the coefficient update state + * machine for the main Tap + * IDLE = 3'b000 + * NOT_UPDATED = 3'b001 + * UPDATE_COEFF = 3'b011 + * MAXIMUM = 3'b010 + * UPDATED = 3'b110 + * MINIMUM = 3'b100 + */ +#define C10GB_LT_STATE_MAIN_OFFSET C10GB_LT_TX_UPDATED_STATUS_REG_OFFSET +#define C10GB_LT_STATE_MAIN_SHIFT (0U) +#define C10GB_LT_STATE_MAIN_MASK BIT_MASK_3_BITS << C10GB_LT_STATE_MAIN_SHIFT + +/** + * Received Coefficient Status Register + */ +#define C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET (0x16U << 2U) + +/** + * New Coefficient Received + * + * A value in this register gives the value of the new coefficient received + * from the link partner + */ +#define C10GB_LT_NEW_RCVD_COEFF_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET +#define C10GB_LT_NEW_RCVD_COEFF_SHIFT (16U) +#define C10GB_LT_NEW_RCVD_COEFF_MASK BIT_MASK_16_BITS << C10GB_LT_NEW_RCVD_COEFF_SHIFT + +/** + * Preset + * + * 1 = Pre-set coefficients + * 0 = Normal operation + */ +#define C10GB_LT_RCVD_COEFF_PRESET_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET +#define C10GB_LT_RCVD_COEFF_PRESET_SHIFT (29U) +#define C10GB_LT_RCVD_COEFF_PRESET_MASK MASK_BIT_29 + +/** + * Initialize + * + * 1 = Initialize coefficients + * 0 = Normal operation + */ +#define C10GB_LT_RCVD_COEFF_INIT_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET +#define C10GB_LT_RCVD_COEFF_INIT_SHIFT (28U) +#define C10GB_LT_RCVD_COEFF_INIT_MASK MASK_BIT_28 + +/** + * Post tap coefficient update + * + * 1 1 = Reserved + * 0 1 = Increment + * 1 0 = Decrement + * 0 0 = Hold + */ +#define C10GB_LT_RCVD_COEFF_POST_UPDATE_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET +#define C10GB_LT_RCVD_COEFF_POST_UPDATE_SHIFT (20U) +#define C10GB_LT_RCVD_COEFF_POST_UPDATE_MASK \ + BIT_MASK_2_BITS << C10GB_LT_RCVD_COEFF_POST_UPDATE_SHIFT + +/** + * Main tap coefficient update + * + * 1 1 = Reserved + * 0 1 = Increment + * 1 0 = Decrement + * 0 0 = Hold + */ +#define C10GB_LT_RCVD_COEFF_MAIN_UPDATE_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET +#define C10GB_LT_RCVD_COEFF_MAIN_UPDATE_SHIFT (18U) +#define C10GB_LT_RCVD_COEFF_MAIN_UPDATE_MASK \ + BIT_MASK_2_BITS << C10GB_LT_RCVD_COEFF_MAIN_UPDATE_SHIFT + +/** + * Pre tap coefficient update + * + * 1 1 = Reserved + * 0 1 = Increment + * 1 0 = Decrement + * 0 0 = Hold + */ +#define C10GB_LT_RCVD_COEFF_PRE_UPDATE_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET +#define C10GB_LT_RCVD_COEFF_PRE_UPDATE_SHIFT (16U) +#define C10GB_LT_RCVD_COEFF_PRE_UPDATE_MASK BIT_MASK_2_BITS << C10GB_LT_RCVD_COEFF_PRE_UPDATE_SHIFT + +/** + * New Status Received + * + * A value in this register gives the value of the new status received from the + * link partner + */ +#define C10GB_LT_NEW_RCVD_STATUS_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET +#define C10GB_LT_NEW_RCVD_STATUS_SHIFT (0U) +#define C10GB_LT_NEW_RCVD_STATUS_MASK BIT_MASK_16_BITS << C10GB_LT_NEW_RCVD_STATUS_SHIFT + +/** + * Receiver Ready + * + * 1 = The remote receiver has determined that training is completed and is + * prepared to receive data. + * 0 = The remote receiver is requesting that training continue. + */ +#define C10GB_LT_RCVD_COEFF_RCVR_READY_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET +#define C10GB_LT_RCVD_COEFF_RCVR_READY_SHIFT (15U) +#define C10GB_LT_RCVD_COEFF_RCVR_READY_MASK MASK_BIT_15 + +/** + * Post tap coefficient value + * + * 1 1 = Maximum + * 1 0 = Minimum + * 0 1 = updated + * 0 0 = Not Updated + */ +#define C10GB_LT_RCVD_COEFF_POST_VALUE_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET +#define C10GB_LT_RCVD_COEFF_POST_VALUE_SHIFT (4U) +#define C10GB_LT_RCVD_COEFF_POST_VALUE_MASK BIT_MASK_2_BITS << C10GB_LT_RCVD_COEFF_POST_VALUE_SHIFT + +/** + * Main tap coefficient value + * + * 1 1 = Maximum + * 1 0 = Minimum + * 0 1 = updated + * 0 0 = Not Updated + */ +#define C10GB_LT_RCVD_COEFF_MAIN_VALUE_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET +#define C10GB_LT_RCVD_COEFF_MAIN_VALUE_SHIFT (2U) +#define C10GB_LT_RCVD_COEFF_MAIN_VALUE_MASK BIT_MASK_2_BITS << C10GB_LT_RCVD_COEFF_MAIN_VALUE_SHIFT + +/** + * Pre tap coefficient value + * + * 1 1 = Maximum + * 1 0 = Minimum + * 0 1 = updated + * 0 0 = Not Updated + */ +#define C10GB_LT_RCVD_COEFF_PRE_VALUE_OFFSET C10GB_LT_RCVD_COEFF_STATUS_REG_OFFSET +#define C10GB_LT_RCVD_COEFF_PRE_VALUE_SHIFT (0U) +#define C10GB_LT_RCVD_COEFF_PRE_VALUE_MASK BIT_MASK_2_BITS << C10GB_LT_RCVD_COEFF_PRE_VALUE_SHIFT + +/** + * TX Coefficient Configuration Register + */ +#define C10GB_LT_TX_COEFF_CFG_REG_OFFSET (0x18U << 2U) + +/** + * Hold Pre Cursor Send + * + * If “1” then hold coefficient is sent to the link partner for pre cursor + */ +#define C10GB_LT_TX_HOLD_PRE_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET +#define C10GB_LT_TX_HOLD_PRE_SHIFT (10U) +#define C10GB_LT_TX_HOLD_PRE_MASK MASK_BIT_10 + +/** + * Decrement Pre Cursor Send + * + * If “1” then the decrement coefficient is sent to the link partner for pre + * cursor + */ +#define C10GB_LT_TX_DEC_PRE_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET +#define C10GB_LT_TX_DEC_PRE_SHIFT (9U) +#define C10GB_LT_TX_DEC_PRE_MASK MASK_BIT_9 + +/** + * Increment Pre Cursor Send + * + * If “1” then the increment coefficient is sent to the link partner for pre + * cursor + */ +#define C10GB_LT_TX_INC_PRE_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET +#define C10GB_LT_TX_INC_PRE_SHIFT (8U) +#define C10GB_LT_TX_INC_PRE_MASK MASK_BIT_8 + +/** + * Hold Post Cursor Send + * + * If “1” then the hold coefficient is sent to the link partner for post + * cursor + */ +#define C10GB_LT_TX_HOLD_POST_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET +#define C10GB_LT_TX_HOLD_POST_SHIFT (6U) +#define C10GB_LT_TX_HOLD_POST_MASK MASK_BIT_6 + +/** + * Decrement Post Cursor Send + * + * If “1” then the decrement coefficient is sent to the link partner for post + * cursor + */ +#define C10GB_LT_TX_DEC_POST_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET +#define C10GB_LT_TX_DEC_POST_SHIFT (5U) +#define C10GB_LT_TX_DEC_POST_MASK MASK_BIT_5 + +/** + * Increment Post Cursor Send + * + * If “1” then the increment coefficient is sent to the link partner for post + * cursor + */ +#define C10GB_LT_TX_INC_POST_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET +#define C10GB_LT_TX_INC_POST_SHIFT (4U) +#define C10GB_LT_TX_INC_POST_MASK MASK_BIT_4 + +/** + * Hold Main Cursor Send + * + * If “1” then the hold coefficient is sent to the link partner for mian + * cursor + */ +#define C10GB_LT_TX_HOLD_MAIN_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET +#define C10GB_LT_TX_HOLD_MAIN_SHIFT (2U) +#define C10GB_LT_TX_HOLD_MAIN_MASK MASK_BIT_2 + +/** + * Decrement Main Cursor Send + * + * If “1” then the decrement coefficient is sent to the link partner for main + * cursor + */ +#define C10GB_LT_TX_DEC_MAIN_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET +#define C10GB_LT_TX_DEC_MAIN_SHIFT (1U) +#define C10GB_LT_TX_DEC_MAIN_MASK MASK_BIT_1 + +/** + * Increment Main Cursor Send + * + * If “1” then the increment coefficient is sent to the link partner for main + * cursor + */ +#define C10GB_LT_TX_INC_MAIN_OFFSET C10GB_LT_TX_COEFF_CFG_REG_OFFSET +#define C10GB_LT_TX_INC_MAIN_SHIFT (0U) +#define C10GB_LT_TX_INC_MAIN_MASK MASK_BIT_0 + +/** + * PRBS error word count register + */ +#define C10GB_LT_PRBS_ERR_WRD_REG_OFFSET (0x1FU << 2U) + +/* + * PRBS error word count + */ +#define C10GB_LT_PRBS_ERR_WRD_CNT_OFFSET C10GB_LT_PRBS_ERR_WRD_REG_OFFSET +#define C10GB_LT_PRBS_ERR_WRD_CNT_SHIFT (0U) +#define C10GB_LT_PRBS_ERR_WRD_CNT_MASK BIT_MASK_32_BITS << C10GB_LT_PRBS_ERR_WRD_CNT_SHIFT + +/** + * 10GBASE-KR Status + */ +#define C10GB_LT_STATUS_REG_OFFSET (0x26U << 2U) + +/** + * RX calibration done + * + * 1’ Indicates remote receiver calibration is done. The Firmware should set + * this bit in response to the RX calibration request. + * This Bit will clear the Bit 2 of this Register. + * + */ +#define C10GB_LT_RX_CAL_DONE_OFFSET C10GB_LT_STATUS_REG_OFFSET +#define C10GB_LT_RX_CAL_DONE_SHIFT (6U) +#define C10GB_LT_RX_CAL_DONE_MASK MASK_BIT_6 + +/** + * Request TX equalization + * + * ‘1’ indicates local receiver is responded for remote receiver rx calibration + * request. + * + */ +#define C10GB_LT_REQ_TX_EQUAL_OFFSET C10GB_LT_STATUS_REG_OFFSET +#define C10GB_LT_REQ_TX_EQUAL_SHIFT (5U) +#define C10GB_LT_REQ_TX_EQUAL_MASK MASK_BIT_5 + +/** + * Signal detect + * + * ‘1’ indicated both local and remote receiver ready. + * + */ +#define C10GB_LT_SIGNAL_DETECT_OFFSET C10GB_LT_STATUS_REG_OFFSET +#define C10GB_LT_SIGNAL_DETECT_SHIFT (4U) +#define C10GB_LT_SIGNAL_DETECT_MASK MASK_BIT_4 + +/** + * Training Fail + * + * ‘1’ indicates 500ms of time is expired during link training + * + */ +#define C10GB_LT_TRAINING_FAIL_OFFSET C10GB_LT_STATUS_REG_OFFSET +#define C10GB_LT_TRAINING_FAIL_SHIFT (3U) +#define C10GB_LT_TRAINING_FAIL_MASK MASK_BIT_3 + +/** + * Request RX calibration + * + * ‘1’ Indicates remote receiver is requested for its calibration + * + */ +#define C10GB_LT_REQ_RX_CAL_OFFSET C10GB_LT_STATUS_REG_OFFSET +#define C10GB_LT_REQ_RX_CAL_SHIFT (2U) +#define C10GB_LT_REQ_RX_CAL_MASK MASK_BIT_2 + +/** + * Link training frame lock + * + * ‘1’ indicates link training frame is detected + * + */ +#define C10GB_LT_FRAME_LOCK_OFFSET C10GB_LT_STATUS_REG_OFFSET +#define C10GB_LT_FRAME_LOCK_SHIFT (1U) +#define C10GB_LT_FRAME_LOCK_MASK MASK_BIT_1 + +/** + * Auto-negotiation good link check + * + * ‘1’ indicates Auto-negotiation is completed + * + */ +#define C10GB_AN_GOOD_CHECK_OFFSET C10GB_LT_STATUS_REG_OFFSET +#define C10GB_AN_GOOD_CHECK_SHIFT (0U) +#define C10GB_AN_GOOD_CHECK_MASK MASK_BIT_0 + +/******************************************************************************/ +/* Core10GBaseKR PHY Transmit Control */ +/******************************************************************************/ + +/** + * Transmit Control Register + */ +#define C10GB_TX_CTRL_REG_OFFSET (0x0U << 2U) + +/** + * PMA Data Select + * + * PMA TX Data Select. Used to select the TX Raw data from the TX Clause Blocks + * to Serdes Interface. + * 2’b00 – PCS Sublayer clause 49 data will be transmitted to the serdes + * interface + * 2’b10 – Auto-negotiation block, PCS sublayer Clause 73 data will be + * transmitted to the serdes interface + * 2’b11 – Link Training block, PCS sublayer Clause 72 data will be transmitted + * to the serdes interface + * 2’b01 – Reserved + + */ +#define C10GB_TX_CTRL_PMA_DATA_OFFSET C10GB_TX_CTRL_REG_OFFSET +#define C10GB_TX_CTRL_PMA_DATA_SHIFT (0U) +#define C10GB_TX_CTRL_PMA_DATA_MASK BIT_MASK_2_BITS << C10GB_TX_CTRL_PMA_DATA_SHIFT + +/** + * XCVR LOS + * + * Loss of sync signal to the XCVR + * 1 - LOS signal is enabled, XCVR will lock to reference + * 0 - LOS signal is disabled, XCVR will lock to data + */ +#define C10GB_TX_CTRL_XCVR_LOS_OFFSET C10GB_TX_CTRL_REG_OFFSET +#define C10GB_TX_CTRL_XCVR_LOS_SHIFT (4U) +#define C10GB_TX_CTRL_XCVR_LOS_MASK MASK_BIT_4 + +/** + * PCS Tx Reset + * + * Soft reset bit for PCS reset + * 1 - TX logic is reset + * 0 - TX logic is not reset + * Self clearing + */ +#define C10GB_TX_CTRL_TX_RESET_OFFSET C10GB_TX_CTRL_REG_OFFSET +#define C10GB_TX_CTRL_TX_RESET_SHIFT (5U) +#define C10GB_TX_CTRL_TX_RESET_MASK MASK_BIT_5 + +/** + * PCS Rx Reset + * + * Soft reset bit for PCS reset + * 1 - RX logic is reset + * 0 - RX logic is not reset + * Self clearing + */ +#define C10GB_TX_CTRL_RX_RESET_OFFSET C10GB_TX_CTRL_REG_OFFSET +#define C10GB_TX_CTRL_RX_RESET_SHIFT (6U) +#define C10GB_TX_CTRL_RX_RESET_MASK MASK_BIT_6 + +/** + * IP version register + */ +#define C10GB_IP_VERSION_REG_OFFSET (0x1U << 2U) + +#define C10GB_IP_VERSION_OFFSET C10GB_IP_VERSION_REG_OFFSET +#define C10GB_IP_VERSION_SHIFT (0U) +#define C10GB_IP_VERSION_MASK BIT_MASK_32_BITS << C10GB_IP_VERSION_SHIFT + +/** + * Major Version + * + * This field provides the major version of the IP. + */ +#define C10GB_IP_VERSION_MAJOR_OFFSET C10GB_IP_VERSION_REG_OFFSET +#define C10GB_IP_VERSION_MAJOR_SHIFT (16U) +#define C10GB_IP_VERSION_MAJOR_MASK BIT_MASK_16_BITS << C10GB_IP_VERSION_MAJOR_SHIFT + +/** + * Minor Version + * + * This field provides the minor version of the IP. + */ +#define C10GB_IP_VERSION_MINOR_OFFSET C10GB_IP_VERSION_REG_OFFSET +#define C10GB_IP_VERSION_MINOR_SHIFT (8U) +#define C10GB_IP_VERSION_MINOR_MASK BIT_MASK_8_BITS << C10GB_IP_VERSION_MINOR_SHIFT + +/** + * Sub Version + * + * This field provides the sub version of the IP. + */ +#define C10GB_IP_VERSION_SUB_OFFSET C10GB_IP_VERSION_REG_OFFSET +#define C10GB_IP_VERSION_SUB_SHIFT (0U) +#define C10GB_IP_VERSION_SUB_MASK BIT_MASK_8_BITS << C10GB_IP_VERSION_SUB_SHIFT + +/** + * FEC user configuration register + */ +#define C10GB_FEC_USE_CFG_REG_OFFSET (0x2U << 2U) + +/** + * FEC user configuration + * + * User has configured FEC Logic as part of the IP + * 0 – FEC Not Configured + * 1 - FEC is Configured + * This register will be read by the software to enable the FEC during the AN + */ +#define C10GB_FEC_USE_CFG_OFFSET C10GB_FEC_USE_CFG_REG_OFFSET +#define C10GB_FEC_USE_CFG_SHIFT (0U) +#define C10GB_FEC_USE_CFG_MASK MASK_BIT_0 + +/******************************************************************************/ +/* Core10GBaseKR PHY Receive Status */ +/******************************************************************************/ + +/** + * Receive Status Register + */ +#define C10GB_RX_STATUS_REG_OFFSET (0x0U << 2U) + +/** + * PCS49 Status + * + * Receive Status signal + * 1 – Receiver has attained Block Lock + * 0 – Receiver has not attained the Block Lock + */ +#define C10GB_RX_STATUS_PCS49_OFFSET C10GB_RX_STATUS_REG_OFFSET +#define C10GB_RX_STATUS_PCS49_SHIFT (0U) +#define C10GB_RX_STATUS_PCS49_MASK BIT_MASK_2_BITS << C10GB_RX_STATUS_PCS49_SHIFT + +/******************************************************************************/ +/* Core10GBaseKR_PHY Memory Map */ +/******************************************************************************/ +#define C10GB_AN_BASE_OFFSET (0x0U << 8U) +#define C10GB_LT_BASE_OFFSET (0x4U << 8U) +#define C10GB_TX_CTRL_BASE_OFFSET (0x8U << 8U) +#define C10GB_RX_STATUS_BASE_OFFSET (0x9U << 8U) + +/// @endcond + +#ifdef __cplusplus +} +#endif + +#endif /* CORE10GBASEKR_PHY_REG_H_ */ diff --git a/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_types.h b/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_types.h new file mode 100644 index 0000000..217e903 --- /dev/null +++ b/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_types.h @@ -0,0 +1,419 @@ +/** + * Copyright 2022 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * @file core10gbasekr_phy_types.h + * @author Microchip FPGA Embedded Systems Solutions + * @brief Core10GBaseKR_PHY Types + * + */ + +#ifndef CORE10GBASEKR_PHY_TYPES_H_ +#define CORE10GBASEKR_PHY_TYPES_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "hal/hal.h" + +/** + * The phy10gkr_error_t enumeration acts as an error lookup. + * + * - PHY10GKR_ERR_USER_CONFIG implies that the config structure is Null. + * - PHY10GKR_ERR_NO_XCVR implies that there is no pointer to an instance of a XCVR. + * - PHY10GKR_ERR_XCVR_API_FUCNTION_POINTER implies that at least one XCVR API + * function pointer is null. + */ +typedef enum __phy_error +{ + PHY10GKR_ERR_USER_CONFIG = 1, + PHY10GKR_ERR_NO_XCVR = 2, + PHY10GKR_ERR_XCVR_API_FUNCTION_POINTER = 3, +} phy10gkr_error_t; + +/** + * The phy10gkr_lane_los_t enumeration identifies the state of the lane loss + * detection. + */ +typedef enum __lane_los_state +{ + LANE_LOS_LOCK_TO_DATA = 0, + LANE_LOS_LOCK_TO_REF = 1 +} phy10gkr_lane_los_t; + +/** + * The phy10gkr_timer_t structure describes the start and end time instance of + * the measurement with the PHY driver. + */ +typedef struct __phy_timer +{ + uint32_t start; + uint32_t end; +} phy10gkr_timer_t; + +/** + * The phy10gkr_an_state_t enumeration is used to identify the state of the auto- + * negotiation arbitration state machine, which is implemented by the + * Core10GBaseKR_PHY. + */ +typedef enum __an_state +{ + ST_AUTO_NEG_ENABLE = 0x0, + ST_TRANSMIT_DISABLE = 0x1, + ST_ABILITY_DETECT = 0x2, + ST_ACKNOWLEDGE_DETECT = 0x3, + ST_COMPLETE_ACKNOWLEDEGE = 0x4, + ST_AN_GOOD_CHECK = 0x5, + ST_AN_GOOD = 0x6, + ST_NEXT_PAGE_WAIT = 0x7, + ST_NEXT_PAGE_WAIT_TX_IDLE = 0x8, + ST_LINK_STATUS_CHECK = 0x9, + ST_PARALLEL_DETECTION_FAULT = 0xA +} phy10gkr_an_state_t; + +/** + * The phy10gkr_an_status_t enumeration specifies the status of auto-negotiation. + */ +typedef enum __an_status +{ + STATUS_AN_INCOMPLETE, + STATUS_AN_COMPLETE +} phy10gkr_an_status_t; + +/** + * The phy10gkr_an_api_state_t enumeration identifies the state of the + * auto-negotiation state machine API. + */ +typedef enum __api_status +{ + AN_API_SM_INIT, + AN_API_SM_STATUS_UPDATE +} phy10gkr_an_api_state_t; + +/** + * The phy10gkr_an_instance_t struct describes an instance of the + * auto-negotiation parameters. + */ +typedef struct __an_instance +{ + phy10gkr_an_state_t state; + phy10gkr_an_api_state_t api_state; + + uint32_t complete_cnt; + phy10gkr_an_status_t status; + + uint64_t adv_ability; + uint64_t lp_bp_adv_ability; +} phy10gkr_an_instance_t; + +/** + * The phy10gkr_lt_state_t enumeration identifies the link training state machine + * state implemented by the Core10GBaseKr_PHY IP block. + */ +typedef enum __lt_state +{ + LT_STATE_IDLE = 0, + LT_STATE_INITIALIZE = 1, + LT_STATE_SEND_TRAINING = 3, + LT_STATE_TRAIN_LOCAL = 2, + LT_STATE_TRAIN_REMOTE = 6, + LT_STATE_LINK_READY = 7, + LT_STATE_SEND_DATA = 5, + LT_STATE_FAILURE = 4 +} phy10gkr_lt_state_t; + +/** + * The phy10gkr_lt_link_status_t enumeration identifies the status and state of + * the link with the link partner. + */ +typedef enum __lt_link_status +{ + STATUS_LT_INCOMPLETE, + STATUS_LT_COMPLETE, + STATUS_LT_LINK_MAINTAINED, + STATUS_LT_FAILURE +} phy10gkr_lt_link_status_t; + +/** + * The phy10gkr_lt_api_state_t enumeration identifies the link training API state + * machine state. + */ +typedef enum __lt_api_status +{ + LT_API_SM_INIT, + LT_API_SM_STATUS_UPDATE +} phy10gkr_lt_api_state_t; + +/** + * The phy10gkr_coeff_update_status_t enumeration identifies the status of the + * coefficient sweep algorithm. + */ +typedef enum coeff_update_status +{ + SWEEP_NOT_STARTED, + SWEEP_START, + SWEEP_INCOMPLETE, + SWEEP_COMPLETE, +} phy10gkr_coeff_update_status_t; + +/** + * The phy10gkr_calirbation_request_t enumeration identifies the initial conditions of a device. For + * example, the local device will calibrate using a preset request. + */ +typedef enum __calirbation_request +{ + C10GBKR_LT_PRESET = 0U, + C10GBKR_LT_INITALISE = 1U +} phy10gkr_calirbation_request_t; + +/** + * The phy10gkr_coeff_status_report_t enumeration identifies the link training + * status report update. + */ +typedef enum coeff_status_report +{ + LT_COEFF_STATUS_NOT_UPDATED = 0U, + LT_COEFF_STATUS_UPDATED = 1U, + LT_COEFF_STATUS_MIN = 2U, + LT_COEFF_STATUS_MAX = 3U +} phy10gkr_coeff_status_report_t; + +/** + * The phy10gkr_tx_equalizer_tap_t enumeration specifies the three different transmitter taps. + */ +typedef enum tx_equalizer_tap +{ + PRE_TAP, + MAIN_TAP, + POST_TAP +} phy10gkr_tx_equalizer_tap_t; + +/** + * The phy10gkr_tap_cal_state_t enumeration specifies the state of the link partner calibration + * algorithm. + */ +typedef enum tap_cal_state +{ + TAP_MAX_CAL, + TAP_MIN_CAL, + TAP_OPTIMISE_CAL +} phy10gkr_tap_cal_state_t; + +/** + * The phy10gkr_local_rxcvr_lock_t enumeration specifies the condition of the + * link partner calibration algorithm. During training, when the link partner has + * been calibrated, the local receiver ready lock is locked and the status report + * is updated to notify the link partner. + */ +typedef enum local_rxcvr_lock +{ + LOCAL_RXCVR_UNLOCKED = 0, + LOCAL_RXCVR_LOCKED = 1 +} phy10gkr_local_rxcvr_lock_t; + +/** + * The phy10gkr_coeff_update_t struct describes an instance of the link training + * coefficient update. This structure supports calibrating the link partners + * transmitter taps. + */ +typedef struct coeff_update +{ + uint32_t cnt; + uint32_t inc_cnt; + uint32_t dec_cnt; + + phy10gkr_tap_cal_state_t lp_tap_cal_state; + + uint32_t optimal_index; + uint32_t optimal_cnt; +} phy10gkr_coeff_update_t; + +/** + * The phy10gkr_lt_instance_t struct describes an instance of the link training + * parameters. + */ +typedef struct __lt_instance +{ + phy10gkr_lt_state_t state; + phy10gkr_lt_api_state_t api_state; + phy10gkr_lt_link_status_t status; + + phy10gkr_timer_t timer; + + uint32_t fail_cnt; + uint32_t complete_cnt; + uint32_t tx_equ_cnt; + uint32_t rx_cal_cnt; + uint32_t sig_cnt; + uint32_t rcvr_cnt; + uint32_t sm_cycle_cnt; + + phy10gkr_tx_equalizer_tap_t lp_cal_sweep_state; + phy10gkr_coeff_update_t main; + phy10gkr_coeff_update_t post; + phy10gkr_coeff_update_t pre; + + phy10gkr_local_rxcvr_lock_t local_rxcvr; +} phy10gkr_lt_instance_t; + +/** + * The phy10gkr_state_t enumeration identifies the state of the 10GBASE-KR state + * machine. + */ +typedef enum __c10gbkr_state +{ + AN_SERDES_CONFIG, + AN_SM, + LT_SERDES_CONFIG, + LT_SM, + LINK_ESTABLISHED_CHECK +} phy10gkr_state_t; + +/** + * The phy10gkr_status_t enumeration identifies the status of the 10GBASE-KR + * state machine. + * + * This enumeration can identify failures encountered by the 10GBASE-KR + * algorithm. + */ +typedef enum __c10gbkr_status +{ + AN_SERDES_CONFIGURATION = 1, + AN_IN_PROGRESS = 2, + AN_COMPLETE = 3, + LT_SERDES_CONFIGURATION = 4, + LT_SERDES_CAL_FAILURE = 5, + LT_SERDES_CAL_COMPLETE = 6, + LT_IN_PROGRESS = 7, + LT_FAILURE = 8, + LINK_BROKEN = 9, + LINK_ESTABLISHED = 0 +} phy10gkr_status_t; + +/** + * The phy10gkr_xcvr_api_t structure identifies the required XCVR APIs that this + * driver requires to complete IEEE802.3 Clause 72 and 73. All function pointers + * require a return value of type uint8_t. Each function that the pointers point to + * require void pointer to an XCVR instance, with the exception of tx_equalization + * which requires three additional parameters, absolute tap coefficients. + * + * - init: Initialise the XCVR which is implemented in the hardware design. + * - auto_neg_data_rate: Configure the XCVR for auto-negotiation. + * - link_training_data_rate: Configure the XCVR for link training. + * - cdr_lock: Check if CDR is locked and return success or failure, where 0 is + * success. + * - ctle_cal: Start CTLE calibration. + * - ctle_cal_status: Check if CTLE is complete and return success or failure, where 0 is + * success. + * - dfe_cal: Start DFE calibration. + * - dfe_cal_status: Check if DFE is complete and return success or failure, where 0 is + * success. + * - reset_pcs_rx: Reset the XCVR PCS RX path. + * - tx_equalization: Set the XCVR coefficients which are passed as parameters, + * where tx_main_tap implies C(0), tx_post_tap implies C(+1) and tx_pre_tap implies + * C(-1). These coefficients are absolute but the XCVR may require the signed + * value. + */ +typedef struct __phy10gkr_xcvr_api +{ + uint8_t (*init)(void *xcvr); + uint8_t (*auto_neg_data_rate)(void *xcvr); + uint8_t (*link_training_data_rate)(void *xcvr); + uint8_t (*cdr_lock)(void *xcvr); + uint8_t (*ctle_cal)(void *xcvr); + uint8_t (*ctle_cal_status)(void *xcvr); + uint8_t (*dfe_cal)(void *xcvr); + uint8_t (*dfe_cal_status)(void *xcvr); + uint8_t (*reset_pcs_rx)(void *xcvr); + uint8_t (*tx_equalization)(void *xcvr, + uint32_t tx_main_tap, + uint32_t tx_post_tap, + uint32_t tx_pre_tap); +} phy10gkr_xcvr_api_t; + +/** + * The phy10gkr_cfg_t struct describes an instance of the Core10GBaseKR_PHY + * configuration parameters. + */ +typedef struct __phy10gkr_cfg +{ + /* XCVR APIs */ + phy10gkr_xcvr_api_t xcvr_api; + + /* PHY Configurations */ + uint32_t fec_request; + + /* Link Training */ + uint32_t rx_calibration_request; + + uint32_t main_preset_tap_coeff; + uint32_t post_preset_tap_coeff; + uint32_t pre_preset_tap_coeff; + + uint32_t main_initialize_tap_coeff; + uint32_t post_initialize_tap_coeff; + uint32_t pre_initialize_tap_coeff; + + uint32_t main_max_tap_ceoff; + uint32_t main_min_tap_ceoff; + uint32_t post_max_tap_ceoff; + uint32_t post_min_tap_ceoff; + uint32_t pre_max_tap_ceoff; + uint32_t pre_min_tap_ceoff; +} phy10gkr_cfg_t; + +/** + * The phy10gkr_instance_t struct describes an instance of the Core10GBaseKR_PHY + * parameters. + */ +typedef struct __phy10gkr_instance +{ + addr_t base_addr; + addr_t an_base_addr; + addr_t lt_base_addr; + addr_t tx_ctrl_base_addr; + addr_t rx_status_base_addr; + + phy10gkr_an_instance_t an; + phy10gkr_lt_instance_t lt; + + phy10gkr_state_t c10gbkr_state; + phy10gkr_status_t c10gbkr_status; + + uint32_t serdes_id; + uint32_t serdes_lane_id; + + uint32_t fec_configured; /* FEC configured in RTL */ + uint32_t fec_negotiated; /* FEC negotiated with link partner */ + + /* Configurations */ + void *xcvr; + phy10gkr_xcvr_api_t xcvr_api; + + uint32_t fec_request; /* Request FEC */ + phy10gkr_calirbation_request_t rx_calibration_request; + + uint32_t main_preset_tap_coeff; + uint32_t post_preset_tap_coeff; + uint32_t pre_preset_tap_coeff; + + uint32_t main_initialize_tap_coeff; + uint32_t post_initialize_tap_coeff; + uint32_t pre_initialize_tap_coeff; + + uint32_t main_max_tap_ceoff; + uint32_t main_min_tap_ceoff; + uint32_t post_max_tap_ceoff; + uint32_t post_min_tap_ceoff; + uint32_t pre_max_tap_ceoff; + uint32_t pre_min_tap_ceoff; +} phy10gkr_instance_t; + +#ifdef __cplusplus +} +#endif + +#endif /* CORE10GBASEKR_PHY_TYPES_H_ */ diff --git a/drivers/fpga_ip/Core10GBaseKR_PHY/phy.h b/drivers/fpga_ip/Core10GBaseKR_PHY/phy.h deleted file mode 100644 index fd15e1d..0000000 --- a/drivers/fpga_ip/Core10GBaseKR_PHY/phy.h +++ /dev/null @@ -1,569 +0,0 @@ -/***************************************************************************//** - * Copyright 2022 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * - * @file phy.h - * @author Microchip FPGA Embedded Systems Solutions - * @brief PHY prototypes - * - */ - -/*=========================================================================*//** - @mainpage Core10GBaseKR_PHY Bare Metal Driver - - ============================================================================== - Introduction - ============================================================================== - Core10GBaseKR_PHY is designed for the IEEE® 802.3-2012 specification and - supports the Core10GBaseKR_PHY interface for Backplane operations. This - configurable core provides the Physical (PHY) layer when used with a - transceiver interface. This IP interfaces with the Ten Gigabit Media - Independent Interface (XGMII) compliant Media Access Control (MAC) at the - system side and the transceiver block at the line side. The physical layer is - designed to work seamlessly with the PolarFire® and PolarFire SoC transceiver - using the Physical Medium Attachment (PMA) mode. This user guide documents the - features provided by the Core10GBaseKR_PHY firmware driver. - - ============================================================================== - Hardware Flow Dependencies - ============================================================================== - This driver covers the configuration details of features such as IEEE802.3 - clauses 73 and 72. - - See the Core10GBaseKR_PHY User Guide for a detailed description of - design requirements when interfacing the Core10GBaseKR_PHY to a transceiver. - - ============================================================================== - Software Flow Dependencies - ============================================================================== - A PHY software configuration file must be included when using this driver. - This will include the macro definition "CORE10GBASEKR_PHY". The purpose of - this file is to configure desired PHY model and to override driver default - values as required. The driver configuration should be stored in a location - away from the driver source code. The following with path is used in our - recommended directory structure: - - \` - /boards//platform_config/driver_config/phy_sw_cfg.h - \` - - ============================================================================== - Theory of Operation - ============================================================================== - The Core10GBaseKR_PHY driver functions are grouped into the following - categories: - - Initialization - - Configuration - - Clause73: Auto-negotiation - - Clause72: Link training - - 10GBASE-KR - - -------------------------------- - Initialization - -------------------------------- - The Core10GBaseKR_PHY driver is initialized through a call to the - PHY10GKR_init() function. The PHY10GKR_init() function must be called before - calling any other Core10GBaseKR_PHY driver functions. - - -------------------------------- - Configuration - -------------------------------- - An instance of the Core10GBaseKR_PHY is configured with a call to the - PHY10GKR_config(). The configuration function resets all the PHY instance - structure members other than information such as performance counters. - Default configurations can be overridden be defining any of the - Core10GBaseKR_PHY constants before loading the driver using a PHY software - configuration file. - - -------------------------------- - Clause73: Auto-negotiation - -------------------------------- - The IEEE802.3 clause 73 auto-negotiation is enabled and executed by calling - PHY10GKR_autonegotiate_sm() function. - - -------------------------------- - Clause72: Link Training - -------------------------------- - The IEEE802.3 clause 72 link training is enabled and executed by a calling - PHY10GKR_link_training_sm(). The Core10GBaseKR_PHY IP and the - Core10GBaseKR_PHY embedded software driver together carry out the link - training. The driver initiates the link training and takes appropriate actions - depending on the events indicated by the 10GBaseKR status register bits during - the link training process. The following figure shows an overview of what - actions are taken for each 10GBaseKR status bit: - - \include resources/link_training_10gbasekr_status.txt - - Training Failure: The training failure bit is set by the IP when the - Core10GBaseKR_PHY link training timer exceeds 500 ms. The driver also - implements a soft timer as an additional protection layer. The - PHY10GKR_get_current_time_ms() function must be overridden by instantiating - this function in user code so that the current time of a timer will be - returned in milli-seconds. When this status is set by Core10GBaseKR_PHY, - the embedded software must reduce the XCVR data rate by calling - PHY10GKR_serdes_an_config() and restart the auto-negotiation state machine by - calling PHY10GKR_autonegotiate_sm(). - - Rx Calibration: The IP sets this status bit to indicate that there is a - received status report of Max/Min/Updated that the Rx calibration algorithm - must handle. The maximum to minimum sweep algorithm described in the - Core10GBaseKR_PHY User Guide is implemented by the functions which are defined - within core10gbasekr_phy_link_training.h. - - After the Rx calibration algorithm completes, the driver updates the - transmit coefficient with new transmitter tap, which will be sent to the - link partner. - - Tx Equalization: This status bit indicates that the received coefficient - update has been updated and that the firmware needs to update the transceiver - transmitter taps. The driver hands off the new coefficient settings to the - transceiver using the PHY10GKR_serdes_tx_equalization() weak function, - which must be overridden. - - Signal Detect: When the driver identifies that this bit has been set by the - Core10GBaseKR_PHY IP, it sets the link training complete flag. The IP updates - this status bit when both the transmitted and received status reports have the - receiver ready bit set. This indicates that both devices have completed their - Rx calibration algorithm. - - -------------------------------- - 10GBASE-KR - -------------------------------- - The full 10GBASE-KR flow is handled by calling PHY10GKR_10gbasekr_sm() - function. As this function is dependent on interacting with a transceiver, - the following weak functions should be overridden for the specific design - being implemented. - - PHY10GKR_get_current_time_ms() - - PHY10GKR_serdes_an_config() - - PHY10GKR_serdes_lt_config() - - PHY10GKR_serdes_cdr_lock() - - PHY10GKR_serdes_dfe_cal() - - PHY10GKR_serdes_tx_equalization() - - *//*=========================================================================*/ -#ifndef PHY_H_ -#define PHY_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "phy_types.h" -#include "core10gbasekr_phy_reg.h" - -#ifdef CORE10GBASEKR_PHY - -/*-------------------------------------------------------------------------*//** - These constant definitions are used as an argument for the function - PHY10GKR_config(). - - */ - -#define MAX_WAIT_TIMER_500MS (161000000U) -#define LT_SOFTWARE_WAIT_TIMER_MS (500U) - -/*-------------------------------------------------------------------------*//** - CORE10GBASEKR_PHY LT MAX/MIN LIMITS - ============================ - The max/min limit constants define the XCVR tap coefficient limits. These - constants can be overridden based on the XCVR, which is integrated into a - specific design. - - Note: Post and Pre tap maximum limits are absolute. - - */ -#ifndef C10GBKR_LT_MAIN_TAP_MAX_LIMIT -#define C10GBKR_LT_MAIN_TAP_MAX_LIMIT (41U) -#endif - -#ifndef C10GBKR_LT_MAIN_TAP_MIN_LIMIT -#define C10GBKR_LT_MAIN_TAP_MIN_LIMIT (26U) -#endif - -#ifndef C10GBKR_LT_POST_TAP_MAX_LIMIT -#define C10GBKR_LT_POST_TAP_MAX_LIMIT (16U) -#endif - -#ifndef C10GBKR_LT_POST_TAP_MIN_LIMIT -#define C10GBKR_LT_POST_TAP_MIN_LIMIT (0U) -#endif - -#ifndef C10GBKR_LT_PRE_TAP_MAX_LIMIT -#define C10GBKR_LT_PRE_TAP_MAX_LIMIT (5U) -#endif - -#ifndef C10GBKR_LT_PRE_TAP_MIN_LIMIT -#define C10GBKR_LT_PRE_TAP_MIN_LIMIT (0U) -#endif - -/*-------------------------------------------------------------------------*//** - CORE10GBASEKR_PHY PRESET - ============================ - The preset constants define the XCVR tap coefficient settings for a preset - request. They can be overridden based on the XCVR, which is integrated into a - specific design. - - Note: Post and Pre tap maximum limits are absolute. - - */ -#ifndef C10GBKR_LT_PRESET_MAIN_TAP -#define C10GBKR_LT_PRESET_MAIN_TAP C10GBKR_LT_MAIN_TAP_MAX_LIMIT -#endif - -#ifndef C10GBKR_LT_PRESET_POST_TAP -#define C10GBKR_LT_PRESET_POST_TAP C10GBKR_LT_POST_TAP_MAX_LIMIT -#endif - -#ifndef C10GBKR_LT_PRESET_PRE_TAP -#define C10GBKR_LT_PRESET_PRE_TAP C10GBKR_LT_PRE_TAP_MAX_LIMIT -#endif - -/*-------------------------------------------------------------------------*//** - CORE10GBASEKR_PHY INIT - ============================ - The initialize constants define the coefficient settings, which is set - when an initialize request is received from the link partner. These constants - should be updated if there is no desire to calibrate the links. - - */ -#ifndef C10GBKR_LT_INITIALIZE_MAIN_TAP -#define C10GBKR_LT_INITIALIZE_MAIN_TAP C10GBKR_LT_MAIN_TAP_MIN_LIMIT -#endif - -#ifndef C10GBKR_LT_INITIALIZE_POST_TAP -#define C10GBKR_LT_INITIALIZE_POST_TAP C10GBKR_LT_POST_TAP_MIN_LIMIT -#endif - -#ifndef C10GBKR_LT_INITIALIZE_PRE_TAP -#define C10GBKR_LT_INITIALIZE_PRE_TAP C10GBKR_LT_PRE_TAP_MIN_LIMIT -#endif - -/*-------------------------------------------------------------------------*//** - CORE10GBASEKR_PHY LP REQUEST - ============================ - This constant defines the request, which will be sent to the link partner and - determines which algorithm will be implemented to calibrate the link partner. - - */ -#ifndef C10GBKR_LT_INITIAL_REQUEST -#define C10GBKR_LT_INITIAL_REQUEST C10GBKR_LT_PRESET -#endif - -/*-------------------------------------------------------------------------*//** - CORE10GBASEKR_PHY AN LINK FAIL INHIBIT TIMER - ============================ - This constant defines the auto-negotiation link fail inhibit timer timeout in - milli-seconds. - - */ -#ifndef C10GBKR_AN_LINK_FAIL_INHITBIT_TIMER -#define C10GBKR_AN_LINK_FAIL_INHITBIT_TIMER\ - (500U) -#endif - -#endif /* CORE10GBASEKR_PHY */ - -/*------------------------Public Function-------------------------------------*/ - -#ifdef CORE10GBASEKR_PHY -/***************************************************************************//** - The PHY10GKR_init() function initializes the Core10GBaseKR_PHY bare-metal - driver. This function sets the base address of the Auto-negotiation, link- - training, tx control, and rx status registers. - - @param this_phy - The this_phy parameter specifies the PHY instance. - - @param base_addr - The base_addr specifies the base address of the IP block. - - @return - This function does not return a value. - - @example - @code - #include "phy.h" - int main(void) - { - PHY10GKR_init(&g_phy, CORE10GBKR_0_PHY_BASE_ADDR); - return (0u); - } - @endcode - */ -void -PHY10GKR_init -( - phy10gkr_instance_t * this_phy, - addr_t base_addr -); - -/***************************************************************************//** - The PHY10GKR_config() function configures the PHY registers with the - predefined defaults and user configurations. This function also resets the - structures back to their initial conditions. - - @param this_phy - The this_phy parameter specifies the PHY instance. - - @return - This function does not return a value. - - @example - @code - #include "phy.h" - int main(void) - { - PHY10GKR_init(&g_phy, CORE10GBKR_0_PHY_BASE_ADDR); - PHY10GKR_config(&g_phy); - return (0u); - } - @endcode - */ -void -PHY10GKR_config -( - phy10gkr_instance_t * this_phy -); - -/***************************************************************************//** - The PHY10GKR_autonegotiate_sm() function enables the auto-negotiation API - state machine, which enables the auto-negotiation registers and then checks the - status of the auto-negotiation state machine to determine if auto-negotiation - has complete. - - @param this_phy - The this_phy parameter specifies the PHY instance. - - @return - This function does not return a value. - - @example - @code - #include "phy.h" - int main(void) - { - PHY10GKR_init(&g_phy, CORE10GBKR_0_PHY_BASE_ADDR); - while(1) - { - PHY10GKR_autonegotiate_sm(&g_phy); - if(STATUS_AN_COMPLETE == g_phy.an.complete) - { - break; - } - } - return (0u); - } - @endcode - */ -void -PHY10GKR_autonegotiate_sm -( - phy10gkr_instance_t * this_phy -); - -/***************************************************************************//** - The PHY10GKR_link_training_sm() function enables the link training API - state machine, which enables the link training registers and then runs the - link training algorithm. - - The connected transceiver must have a data rate of 10 Gbps and locked to a - link partner with the same data rate for successful link training. - - @param this_phy - The this_phy parameter specifies the PHY instance. - - @return - This function does not return a value. - - @example - @code - #include "phy.h" - int main(void) - { - PHY10GKR_init(&g_phy, CORE10GBKR_0_PHY_BASE_ADDR); - while(1) - { - PHY10GKR_link_training_sm(&g_phy); - if(STATUS_LT_FAILURE == g_phy.lt.status) - { - HAL_ASSERT(0); - } - } - return (0u); - } - @endcode - */ -void -PHY10GKR_link_training_sm -( - phy10gkr_instance_t * this_phy -); - -/***************************************************************************//** - The PHY10GKR_10gbasekr_sm() executes the full 10GBASE-KR flow required to - complete the auto-negotiation and link training. - - The 10GBASE-KR status enumeration allows the user to debug the auto-negotiation - and link training algorithms. - - @param this_phy - The this_phy parameter specifies the PHY instance. - - @return - This function returns a state machine status. - - @example - @code - #include "phy.h" - int main(void) - { - uint32_t status; - PHY10GKR_init(&g_phy, CORE10GBKR_0_PHY_BASE_ADDR); - while(1) - { - status = PHY10GKR_10gbasekr_sm(&g_phy); - if(LINK_ESTABLISHED == status) - { - break; - } - } - return (0u); - } - @endcode - */ -uint32_t -PHY10GKR_10gbasekr_sm -( - phy10gkr_instance_t * this_phy -); - -/***************************************************************************//** - The PHY10GKR_set_lane_los_signal() asserts and deasserts the transceivers - Lane Loss of signal detection. - - @param state - Asserts or deasserts the lane LOS - - @return - This function does not return a value. - */ -void -PHY10GKR_set_lane_los_signal -( - phy10gkr_instance_t * this_phy, - uint32_t state -); - -/***************************************************************************//** - The PHY10GKR_get_current_time_ms() is a weak function that can be overridden - by the user to get the current time in milli-seconds. - - @return - This function returns the time in milli-seconds. - */ -uint32_t __attribute__((weak)) -PHY10GKR_get_current_time_ms -( - void -); - -/***************************************************************************//** - The PHY10GKR_serdes_an_config() is a weak function that can be overridden - by the user to configure the XCVR instance integrated in their design - for auto-negotiation. - - @return - This function does not return a value. - */ -void __attribute__((weak)) -PHY10GKR_serdes_an_config -( - void -); - -/***************************************************************************//** - The PHY10GKR_serdes_lt_config() is a weak function that can be overridden - by the user to configure the XCVR instance integrated in their design - for link training at 10 Gbps. - - @return - This function does not return a value. - */ -uint32_t __attribute__((weak)) -PHY10GKR_serdes_lt_config -( - void -); - -/***************************************************************************//** - The PHY10GKR_serdes_cdr_lock() is a weak function that can be overridden by - the user to determine that the XCVR instance integrated has achieved a CDR - lock. - - @return - This function returns 0 on success and 1 on failure. - */ -uint32_t __attribute__((weak)) -PHY10GKR_serdes_cdr_lock -( - void -); - -/***************************************************************************//** - The PHY10GKR_serdes_dfe_cal() is a weak function that can be overridden by - the user to determine that the XCVR instance integrated has completed DFE - calibration. - - Note this function should constantly check if the link training - failure time has timeout and if so exit the function. - - @return - This function does not return a value. - */ -uint32_t __attribute__((weak)) -PHY10GKR_serdes_dfe_cal -( - void -); - -/***************************************************************************//** - The PHY10GKR_serdes_tx_equalization() is a weak function that can be - overridden by the user to set the current XCVR tap coefficients. - - @return - This function does not return a value. - */ -void __attribute__((weak)) -PHY10GKR_serdes_tx_equalization -( - uint32_t tx_main_tap, - uint32_t tx_post_tap, - uint32_t tx_pre_tap -); - -#endif /* CORE10GBASEKR_PHY */ - -#ifdef __cplusplus -} -#endif - -#endif /* PHY_H_ */ diff --git a/drivers/fpga_ip/Core10GBaseKR_PHY/phy_types.h b/drivers/fpga_ip/Core10GBaseKR_PHY/phy_types.h deleted file mode 100644 index 3b09458..0000000 --- a/drivers/fpga_ip/Core10GBaseKR_PHY/phy_types.h +++ /dev/null @@ -1,337 +0,0 @@ -/***************************************************************************//** - * Copyright 2022 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * - * @file phy_types.h - * @author Microchip FPGA Embedded Systems Solutions - * @brief PHY types - * - */ - -#ifndef PHY_TYPES_H_ -#define PHY_TYPES_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include "platform_config/driver_config/phy_sw_cfg.h" -#include "hal/hal.h" - -#ifdef CORE10GBASEKR_PHY -/***************************************************************************//** - The phy10gkr_lane_los_t enumeration identifies the state of the lane loss - detection. - */ -typedef enum __lane_los_state -{ - LANE_LOS_LOCK_TO_DATA = 0, - LANE_LOS_LOCK_TO_REF = 1 -} phy10gkr_lane_los_t; - -/***************************************************************************//** - The phy10gkr_timer_t structure describes the start and end time instance of - the measurement with the PHY driver. - */ -typedef struct __phy_timer -{ - uint32_t start; - uint32_t end; -} phy10gkr_timer_t; - -/***************************************************************************//** - The phy10gkr_an_state_t enumeration is used to identify the state of the auto- - negotiation arbitration state machine, which is implemented by the - Core10GBaseKR_PHY. - */ -typedef enum __an_state -{ - ST_AUTO_NEG_ENABLE = 0x0, - ST_TRANSMIT_DISABLE = 0x1, - ST_ABILITY_DETECT = 0x2, - ST_ACKNOWLEDGE_DETECT = 0x3, - ST_COMPLETE_ACKNOWLEDEGE = 0x4, - ST_AN_GOOD_CHECK = 0x5, - ST_AN_GOOD = 0x6, - ST_NEXT_PAGE_WAIT = 0x7, - ST_NEXT_PAGE_WAIT_TX_IDLE = 0x8, - ST_LINK_STATUS_CHECK = 0x9, - ST_PARALLEL_DETECTION_FAULT = 0xA -} phy10gkr_an_state_t; - -/***************************************************************************//** - The phy10gkr_an_status_t enumeration specifies the status of auto-negotiation. - */ -typedef enum __an_status -{ - STATUS_AN_INCOMPLETE, - STATUS_AN_COMPLETE -} phy10gkr_an_status_t; - -/***************************************************************************//** - The phy10gkr_an_api_state_t enumeration identifies the state of the - auto-negotiation state machine API. - */ -typedef enum __api_status -{ - AN_API_SM_INIT, - AN_API_SM_STATUS_UPDATE -} phy10gkr_an_api_state_t; - -/***************************************************************************//** - The phy10gkr_an_instance_t struct describes an instance of the - auto-negotiation parameters. - */ -typedef struct __an_instance -{ - phy10gkr_an_state_t state; - phy10gkr_an_api_state_t api_state; - - uint32_t complete_cnt; - phy10gkr_an_status_t status; -} phy10gkr_an_instance_t; - -/***************************************************************************//** - The phy10gkr_lt_state_t enumeration identifies the link training state machine - state implemented by the Core10GBaseKr_PHY IP block. - */ -typedef enum __lt_state -{ - LT_STATE_IDLE = 0, - LT_STATE_INITIALIZE = 1, - LT_STATE_SEND_TRAINING = 3, - LT_STATE_TRAIN_LOCAL = 2, - LT_STATE_TRAIN_REMOTE = 6, - LT_STATE_LINK_READY = 7, - LT_STATE_SEND_DATA = 5, - LT_STATE_FAILURE = 4 -} phy10gkr_lt_state_t; - -/***************************************************************************//** - The phy10gkr_lt_link_status_t enumeration identifies the status and state of - the link with the link partner. - */ -typedef enum __lt_link_status -{ - STATUS_LT_INCOMPLETE, - STATUS_LT_COMPLETE, - STATUS_LT_LINK_MAINTAINED, - STATUS_LT_FAILURE -} phy10gkr_lt_link_status_t; - -/***************************************************************************//** - The phy10gkr_lt_api_state_t enumeration identifies the link training API state - machine state. - */ -typedef enum __lt_api_status -{ - LT_API_SM_INIT, - LT_API_SM_STATUS_UPDATE -} phy10gkr_lt_api_state_t; - -/***************************************************************************//** - The phy10gkr_coeff_update_status_t enumeration identifies the status of the - coefficient sweep algorithm. - */ -typedef enum coeff_update_status -{ - SWEEP_NOT_STARTED, - SWEEP_START, - SWEEP_INCOMPLETE, - SWEEP_COMPLETE, -} phy10gkr_coeff_update_status_t; - -/***************************************************************************//** - This enumeration identifies the initial conditions of a device. For example, - the local device will calibrate using a preset request. - */ -typedef enum __calirbation_request -{ - C10GBKR_LT_PRESET = 0U, - C10GBKR_LT_INITALISE = 1U -} phy10gkr_calirbation_request_t; - -/***************************************************************************//** - The phy10gkr_coeff_status_report_t enumeration identifies the link training - status report update. - */ -typedef enum coeff_status_report -{ - LT_COEFF_STATUS_NOT_UPDATED = 0U, - LT_COEFF_STATUS_UPDATED = 1U, - LT_COEFF_STATUS_MIN = 2U, - LT_COEFF_STATUS_MAX = 3U -} phy10gkr_coeff_status_report_t; - -/***************************************************************************//** - This enumeration specifies the three different transmitter taps. - */ -typedef enum tx_equalizer_tap -{ - PRE_TAP, - MAIN_TAP, - POST_TAP -} phy10gkr_tx_equalizer_tap_t; - -/***************************************************************************//** - This enumeration specifies the state of the link partner calibration - algorithm. - */ -typedef enum tap_cal_state -{ - TAP_MAX_CAL, - TAP_MIN_CAL, - TAP_OPTIMISE_CAL -} phy10gkr_tap_cal_state_t; - -/***************************************************************************//** - This enumeration specifies the condition of the link partner calibration - algorithm. During training, when the link partner has been calibrated, the - local receiver ready lock get locked and the status report will be updated - to notify the link partner. - */ -typedef enum local_rxcvr_lock -{ - LOCAL_RXCVR_UNLOCKED = 0, - LOCAL_RXCVR_LOCKED = 1 -} phy10gkr_local_rxcvr_lock_t; - -/***************************************************************************//** - The coeff_update_t struct describes an instance of the link training - coefficient update. This structure supports calibrating the link partners - transmitter taps. - */ -typedef struct coeff_update -{ - uint32_t cnt; - uint32_t inc_cnt; - uint32_t hold_cnt; - uint32_t dec_cnt; - uint32_t max_cnt; - uint32_t min_cnt; - uint32_t update_cnt; - uint32_t no_update_cnt; - uint32_t done_cnt; - uint32_t index; - phy10gkr_coeff_update_status_t status; - - phy10gkr_tap_cal_state_t lp_tap_cal_state; - - uint32_t optimal_index; - uint32_t optimal_cnt; -} phy10gkr_coeff_update_t; - -/***************************************************************************//** - The an_instance_t struct describes an instance of the link training - parameters. - */ -typedef struct __lt_instance -{ - phy10gkr_lt_state_t state; - phy10gkr_lt_api_state_t api_state; - phy10gkr_lt_link_status_t status; - - phy10gkr_timer_t timer; - - phy10gkr_calirbation_request_t tx_request; - phy10gkr_calirbation_request_t rx_request; - - uint32_t fail_cnt; - uint32_t complete_cnt; - uint32_t tx_equ_cnt; - uint32_t rx_cal_cnt; - uint32_t sig_cnt; - uint32_t rcvr_cnt; - - uint32_t sm_cycle_cnt; - - phy10gkr_tx_equalizer_tap_t lp_cal_sweep_state; - phy10gkr_coeff_update_t main; - phy10gkr_coeff_update_t post; - phy10gkr_coeff_update_t pre; - - phy10gkr_local_rxcvr_lock_t local_rxcvr; -} phy10gkr_lt_instance_t; - -/***************************************************************************//** - The c10gbkr_state_t enumeration identifies the state of the 10GBASE-KR state - machine. - */ -typedef enum __c10gbkr_state -{ - AN_SERDES_CONFIG, - AN_SM, - LT_SERDES_CONFIG, - LT_SM, - LINK_ESTABLISHED_CHECK -} phy10gkr_state_t; - -/***************************************************************************//** - The c10gbkr_status_t enumeration identifies the status of the 10GBASE-KR - state machine. - - This enumeration can identify failures encountered by the 10GBASE-KR - algorithm. - */ -typedef enum __c10gbkr_status -{ - AN_SERDES_CONFIGURATION = 1, - AN_IN_PROGRESS = 2, - AN_COMPLETE = 3, - LT_SERDES_CONFIGURATION = 4, - LT_SERDES_CAL_FAILURE = 5, - LT_SERDES_CAL_COMPLETE = 6, - LT_IN_PROGRESS = 7, - LT_FAILURE = 8, - LINK_BROKEN = 9, - LINK_ESTABLISHED = 0 -} phy10gkr_status_t; - -/***************************************************************************//** - The phy10gkr_instance_t struct describes an instance of the Core10GBaseKR_PHY - parameters. - */ -typedef struct __phy10gkr_instance -{ - addr_t base_addr; - addr_t an_base_addr; - addr_t lt_base_addr; - addr_t tx_ctrl_base_addr; - addr_t rx_status_base_addr; - - phy10gkr_an_instance_t an; - phy10gkr_lt_instance_t lt; - - phy10gkr_state_t c10gbkr_state; - phy10gkr_status_t c10gbkr_status; - - uint32_t serdes_id; - uint32_t serdes_lane_id; -} phy10gkr_instance_t; -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* PHY_TYPES_H_ */ diff --git a/drivers/fpga_ip/Core10GBaseKR_PHY/resources/link_training_10gbasekr_status.txt b/drivers/fpga_ip/Core10GBaseKR_PHY/resources/link_training_10gbasekr_status.txt deleted file mode 100644 index 5948625..0000000 --- a/drivers/fpga_ip/Core10GBaseKR_PHY/resources/link_training_10gbasekr_status.txt +++ /dev/null @@ -1,28 +0,0 @@ -
-%%{init : {"flowchart" : {"curve" : "linear", "useMaxWidth" : false, "useMaxHeight" : false, "nodeSpacing" : 30, "rankSpacing" : 40 }}}%% - flowchart TB - Start[/10GBASE-KR Status Register\] --> Rx[Rx Calibration] - Start --> Tx[Tx Equalization] - Start --> Fail[Fail] - Start --> Signal[Signal Detect] - - Fail --> LTFail[LT Failure] - - Rx --> IntRx[Set RX Calibration Bit to Clear Status Bit] - IntRx --> Algo[Max/Min Tap Sweep Algorithm] - Algo --> TxCU[Update the Tx Coefficient Update] - - Tx --> SerdesTX[Pass Rx Coefficient Update to Serdes] - SerdesTX --> TxSR[Update Tx Status Report] - TxSR --> TxDone[Set Tx Equalization Done to Clear Status Bit] - - Signal --> LTComp[LT Complete] - -
- - \ No newline at end of file diff --git a/drivers/fpga_ip/Core10GBaseKR_PHY/uint_32_bit_masks.h b/drivers/fpga_ip/Core10GBaseKR_PHY/uint_32_bit_masks.h index 4826dec..70c5f23 100644 --- a/drivers/fpga_ip/Core10GBaseKR_PHY/uint_32_bit_masks.h +++ b/drivers/fpga_ip/Core10GBaseKR_PHY/uint_32_bit_masks.h @@ -1,30 +1,12 @@ -/***************************************************************************//** +/** * Copyright 2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * * @file uint_32_bit_masks.h * @author Microchip FPGA Embedded Systems Solutions * @brief unsigned 32 bit masks - * + * */ #ifndef UNIT_32_BIT_MASKS_H_ @@ -34,78 +16,76 @@ extern "C" { #endif -/* +/** * Single Bit Mask */ -#define MASK_BIT_31 ((uint32_t)(0x80000000UL)) -#define MASK_BIT_30 ((uint32_t)(0x40000000UL)) -#define MASK_BIT_29 ((uint32_t)(0x20000000UL)) -#define MASK_BIT_28 ((uint32_t)(0x10000000UL)) -#define MASK_BIT_27 ((uint32_t)(0x08000000UL)) -#define MASK_BIT_26 ((uint32_t)(0x04000000UL)) -#define MASK_BIT_25 ((uint32_t)(0x02000000UL)) -#define MASK_BIT_24 ((uint32_t)(0x01000000UL)) -#define MASK_BIT_23 ((uint32_t)(0x00800000UL)) -#define MASK_BIT_22 ((uint32_t)(0x00400000UL)) -#define MASK_BIT_21 ((uint32_t)(0x00200000UL)) -#define MASK_BIT_20 ((uint32_t)(0x00100000UL)) -#define MASK_BIT_19 ((uint32_t)(0x00080000UL)) -#define MASK_BIT_18 ((uint32_t)(0x00040000UL)) -#define MASK_BIT_17 ((uint32_t)(0x00020000UL)) -#define MASK_BIT_16 ((uint32_t)(0x00010000UL)) -#define MASK_BIT_15 ((uint32_t)(0x00008000UL)) -#define MASK_BIT_14 ((uint32_t)(0x00004000UL)) -#define MASK_BIT_13 ((uint32_t)(0x00002000UL)) -#define MASK_BIT_12 ((uint32_t)(0x00001000UL)) -#define MASK_BIT_11 ((uint32_t)(0x00000800UL)) -#define MASK_BIT_10 ((uint32_t)(0x00000400UL)) -#define MASK_BIT_9 ((uint32_t)(0x00000200UL)) -#define MASK_BIT_8 ((uint32_t)(0x00000100UL)) -#define MASK_BIT_7 ((uint32_t)(0x00000080UL)) -#define MASK_BIT_6 ((uint32_t)(0x00000040UL)) -#define MASK_BIT_5 ((uint32_t)(0x00000020UL)) -#define MASK_BIT_4 ((uint32_t)(0x00000010UL)) -#define MASK_BIT_3 ((uint32_t)(0x00000008UL)) -#define MASK_BIT_2 ((uint32_t)(0x00000004UL)) -#define MASK_BIT_1 ((uint32_t)(0x00000002UL)) -#define MASK_BIT_0 ((uint32_t)(0x00000001UL)) +#define MASK_BIT_31 ((uint32_t)(0x80000000UL)) +#define MASK_BIT_30 ((uint32_t)(0x40000000UL)) +#define MASK_BIT_29 ((uint32_t)(0x20000000UL)) +#define MASK_BIT_28 ((uint32_t)(0x10000000UL)) +#define MASK_BIT_27 ((uint32_t)(0x08000000UL)) +#define MASK_BIT_26 ((uint32_t)(0x04000000UL)) +#define MASK_BIT_25 ((uint32_t)(0x02000000UL)) +#define MASK_BIT_24 ((uint32_t)(0x01000000UL)) +#define MASK_BIT_23 ((uint32_t)(0x00800000UL)) +#define MASK_BIT_22 ((uint32_t)(0x00400000UL)) +#define MASK_BIT_21 ((uint32_t)(0x00200000UL)) +#define MASK_BIT_20 ((uint32_t)(0x00100000UL)) +#define MASK_BIT_19 ((uint32_t)(0x00080000UL)) +#define MASK_BIT_18 ((uint32_t)(0x00040000UL)) +#define MASK_BIT_17 ((uint32_t)(0x00020000UL)) +#define MASK_BIT_16 ((uint32_t)(0x00010000UL)) +#define MASK_BIT_15 ((uint32_t)(0x00008000UL)) +#define MASK_BIT_14 ((uint32_t)(0x00004000UL)) +#define MASK_BIT_13 ((uint32_t)(0x00002000UL)) +#define MASK_BIT_12 ((uint32_t)(0x00001000UL)) +#define MASK_BIT_11 ((uint32_t)(0x00000800UL)) +#define MASK_BIT_10 ((uint32_t)(0x00000400UL)) +#define MASK_BIT_9 ((uint32_t)(0x00000200UL)) +#define MASK_BIT_8 ((uint32_t)(0x00000100UL)) +#define MASK_BIT_7 ((uint32_t)(0x00000080UL)) +#define MASK_BIT_6 ((uint32_t)(0x00000040UL)) +#define MASK_BIT_5 ((uint32_t)(0x00000020UL)) +#define MASK_BIT_4 ((uint32_t)(0x00000010UL)) +#define MASK_BIT_3 ((uint32_t)(0x00000008UL)) +#define MASK_BIT_2 ((uint32_t)(0x00000004UL)) +#define MASK_BIT_1 ((uint32_t)(0x00000002UL)) +#define MASK_BIT_0 ((uint32_t)(0x00000001UL)) -/* +/** * Multi Bit Mask */ -#define BIT_MASK_32_BITS ((uint32_t)(0xFFFFFFFFUL)) -#define BIT_MASK_31_BITS ((uint32_t)(0x7FFFFFFFUL)) -#define BIT_MASK_30_BITS ((uint32_t)(0x3FFFFFFFUL)) -#define BIT_MASK_29_BITS ((uint32_t)(0x1FFFFFFFUL)) -#define BIT_MASK_28_BITS ((uint32_t)(0x0FFFFFFFUL)) -#define BIT_MASK_27_BITS ((uint32_t)(0x07FFFFFFUL)) -#define BIT_MASK_26_BITS ((uint32_t)(0x03FFFFFFUL)) -#define BIT_MASK_25_BITS ((uint32_t)(0x01FFFFFFUL)) -#define BIT_MASK_24_BITS ((uint32_t)(0x00FFFFFFUL)) -#define BIT_MASK_23_BITS ((uint32_t)(0x007FFFFFUL)) -#define BIT_MASK_22_BITS ((uint32_t)(0x003FFFFFUL)) -#define BIT_MASK_21_BITS ((uint32_t)(0x001FFFFFUL)) -#define BIT_MASK_20_BITS ((uint32_t)(0x000FFFFFUL)) -#define BIT_MASK_19_BITS ((uint32_t)(0x0007FFFFUL)) -#define BIT_MASK_18_BITS ((uint32_t)(0x0003FFFFUL)) -#define BIT_MASK_17_BITS ((uint32_t)(0x0001FFFFUL)) -#define BIT_MASK_16_BITS ((uint32_t)(0x0000FFFFUL)) -#define BIT_MASK_15_BITS ((uint32_t)(0x00007FFFUL)) -#define BIT_MASK_14_BITS ((uint32_t)(0x00003FFFUL)) -#define BIT_MASK_13_BITS ((uint32_t)(0x00001FFFUL)) -#define BIT_MASK_12_BITS ((uint32_t)(0x00000FFFUL)) -#define BIT_MASK_11_BITS ((uint32_t)(0x000007FFUL)) -#define BIT_MASK_10_BITS ((uint32_t)(0x000003FFUL)) -#define BIT_MASK_9_BITS ((uint32_t)(0x000001FFUL)) -#define BIT_MASK_8_BITS ((uint32_t)(0x000000FFUL)) -#define BIT_MASK_7_BITS ((uint32_t)(0x0000007FUL)) -#define BIT_MASK_6_BITS ((uint32_t)(0x0000003FUL)) -#define BIT_MASK_5_BITS ((uint32_t)(0x0000001FUL)) -#define BIT_MASK_4_BITS ((uint32_t)(0x0000000FUL)) -#define BIT_MASK_3_BITS ((uint32_t)(0x00000007UL)) -#define BIT_MASK_2_BITS ((uint32_t)(0x00000003UL)) - - +#define BIT_MASK_32_BITS ((uint32_t)(0xFFFFFFFFUL)) +#define BIT_MASK_31_BITS ((uint32_t)(0x7FFFFFFFUL)) +#define BIT_MASK_30_BITS ((uint32_t)(0x3FFFFFFFUL)) +#define BIT_MASK_29_BITS ((uint32_t)(0x1FFFFFFFUL)) +#define BIT_MASK_28_BITS ((uint32_t)(0x0FFFFFFFUL)) +#define BIT_MASK_27_BITS ((uint32_t)(0x07FFFFFFUL)) +#define BIT_MASK_26_BITS ((uint32_t)(0x03FFFFFFUL)) +#define BIT_MASK_25_BITS ((uint32_t)(0x01FFFFFFUL)) +#define BIT_MASK_24_BITS ((uint32_t)(0x00FFFFFFUL)) +#define BIT_MASK_23_BITS ((uint32_t)(0x007FFFFFUL)) +#define BIT_MASK_22_BITS ((uint32_t)(0x003FFFFFUL)) +#define BIT_MASK_21_BITS ((uint32_t)(0x001FFFFFUL)) +#define BIT_MASK_20_BITS ((uint32_t)(0x000FFFFFUL)) +#define BIT_MASK_19_BITS ((uint32_t)(0x0007FFFFUL)) +#define BIT_MASK_18_BITS ((uint32_t)(0x0003FFFFUL)) +#define BIT_MASK_17_BITS ((uint32_t)(0x0001FFFFUL)) +#define BIT_MASK_16_BITS ((uint32_t)(0x0000FFFFUL)) +#define BIT_MASK_15_BITS ((uint32_t)(0x00007FFFUL)) +#define BIT_MASK_14_BITS ((uint32_t)(0x00003FFFUL)) +#define BIT_MASK_13_BITS ((uint32_t)(0x00001FFFUL)) +#define BIT_MASK_12_BITS ((uint32_t)(0x00000FFFUL)) +#define BIT_MASK_11_BITS ((uint32_t)(0x000007FFUL)) +#define BIT_MASK_10_BITS ((uint32_t)(0x000003FFUL)) +#define BIT_MASK_9_BITS ((uint32_t)(0x000001FFUL)) +#define BIT_MASK_8_BITS ((uint32_t)(0x000000FFUL)) +#define BIT_MASK_7_BITS ((uint32_t)(0x0000007FUL)) +#define BIT_MASK_6_BITS ((uint32_t)(0x0000003FUL)) +#define BIT_MASK_5_BITS ((uint32_t)(0x0000001FUL)) +#define BIT_MASK_4_BITS ((uint32_t)(0x0000000FUL)) +#define BIT_MASK_3_BITS ((uint32_t)(0x00000007UL)) +#define BIT_MASK_2_BITS ((uint32_t)(0x00000003UL)) #ifdef __cplusplus }