Possible to round trip File -> AST -> JSON -> AST -> File?

[eteran]

Basically what I'm looking to do is to be able to perform arbitrary transformations of the code based on config file rules. My thought is that it's pretty easy to serialize the AST to JSON. Then the tool could just edit the JSON as needed and then (ideally), it could then convert the JSON back to an AST and print it to a file.

I know that if we have an AST object that we can emit a file, so I think the only piece that I don't know how to do with the given API is the JSON -> AST part.

Is this something that is supported directly? Would it be hard to implement manually if not?

[MikePopoloski]

To answer your question directly, there isn't currently any functionality to parse JSON and turn it into an AST. Such a thing is of course possible but it would require a fair amount of work.

Also to further clarify, the AST itself doesn't turn back into Verilog code nicely. The AST is "abstract" in the sense that it no longer directly represents what the user typed, so for example various input forms get normalized into one representation in the AST. The "concerete" syntax tree (in slang represented by SyntaxNode and Token objects, encapsulated in the SyntaxTree class) does round trip back to source code as an explicit design goal, but there isn't currently a way to turn that tree into JSON (although adding one would be fairly easy).