ALU.syr

Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.06 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.06 secs
 
--> Reading design: ALU.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "ALU.prj"
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "ALU"
Output Format                      : NGC
Target Device                      : xc7a100t-3-csg324

---- Source Options
Top Module Name                    : ALU
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 32
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "D:\Mina\Term 6\Computer Archetcture\Project_28_2\ALU.vhd" into library work
Parsing entity <ALU>.
Parsing architecture <Behavioral> of entity <alu>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <ALU> (architecture <Behavioral>) from library <work>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ALU>.
    Related source file is "D:\Mina\Term 6\Computer Archetcture\Project_28_2\ALU.vhd".
    Found 32-bit adder for signal <A[31]_B[31]_add_9_OUT> created at line 43.
    Found 32-bit subtractor for signal <GND_5_o_GND_5_o_sub_12_OUT<31:0>> created at line 46.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<30>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<29>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<28>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<27>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<26>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<25>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<24>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<23>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<22>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<21>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<20>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<19>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<18>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<17>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<16>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<15>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<14>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<13>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Res<31>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Found 32-bit comparator equal for signal <Zero> created at line 22
    Found 32-bit comparator greater for signal <A[31]_B[31]_LessThan_7_o> created at line 36
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  32 Latch(s).
	inferred   2 Comparator(s).
	inferred 224 Multiplexer(s).
Unit <ALU> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 32-bit adder                                          : 1
 32-bit subtractor                                     : 1
# Latches                                              : 32
 1-bit latch                                           : 32
# Comparators                                          : 2
 32-bit comparator equal                               : 1
 32-bit comparator greater                             : 1
# Multiplexers                                         : 224
 1-bit 2-to-1 multiplexer                              : 224

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 32-bit adder                                          : 1
 32-bit subtractor                                     : 1
# Comparators                                          : 2
 32-bit comparator equal                               : 1
 32-bit comparator greater                             : 1
# Multiplexers                                         : 224
 1-bit 2-to-1 multiplexer                              : 224

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <ALU> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ALU, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : ALU.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 357
#      GND                         : 1
#      LUT2                        : 64
#      LUT3                        : 31
#      LUT4                        : 64
#      LUT5                        : 3
#      LUT6                        : 41
#      MUXCY                       : 88
#      VCC                         : 1
#      XORCY                       : 64
# FlipFlops/Latches                : 32
#      LD                          : 32
# Clock Buffers                    : 1
#      BUFG                        : 1
# IO Buffers                       : 101
#      IBUF                        : 68
#      OBUF                        : 33

Device utilization summary:
---------------------------

Selected Device : 7a100tcsg324-3 


Slice Logic Utilization: 
 Number of Slice LUTs:                  203  out of  63400     0%  
    Number used as Logic:               203  out of  63400     0%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:    203
   Number with an unused Flip Flop:     203  out of    203   100%  
   Number with an unused LUT:             0  out of    203     0%  
   Number of fully used LUT-FF pairs:     0  out of    203     0%  
   Number of unique control sets:         1

IO Utilization: 
 Number of IOs:                         101
 Number of bonded IOBs:                 101  out of    210    48%  
    IOB Flip Flops/Latches:              32

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-------------------------------------------------------+------------------------+-------+
Clock Signal                                           | Clock buffer(FF name)  | Load  |
-------------------------------------------------------+------------------------+-------+
ALUop[3]_ALUop[3]_OR_71_o(ALUop[3]_ALUop[3]_OR_71_o1:O)| BUFG(*)(Res_31)        | 32    |
-------------------------------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: No path found
   Minimum input arrival time before clock: 3.091ns
   Maximum output required time after clock: 0.751ns
   Maximum combinational path delay: 1.912ns

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'ALUop[3]_ALUop[3]_OR_71_o'
  Total number of paths / destination ports: 3516 / 32
-------------------------------------------------------------------------
Offset:              3.091ns (Levels of Logic = 36)
  Source:            A<0> (PAD)
  Destination:       Res_31 (LATCH)
  Destination Clock: ALUop[3]_ALUop[3]_OR_71_o falling

  Data Path: A<0> to Res_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             7   0.001   0.407  A_0_IBUF (A_0_IBUF)
     LUT2:I0->O            1   0.097   0.000  Madd_A[31]_B[31]_add_9_OUT_lut<0> (Madd_A[31]_B[31]_add_9_OUT_lut<0>)
     MUXCY:S->O            1   0.353   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<0> (Madd_A[31]_B[31]_add_9_OUT_cy<0>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<1> (Madd_A[31]_B[31]_add_9_OUT_cy<1>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<2> (Madd_A[31]_B[31]_add_9_OUT_cy<2>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<3> (Madd_A[31]_B[31]_add_9_OUT_cy<3>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<4> (Madd_A[31]_B[31]_add_9_OUT_cy<4>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<5> (Madd_A[31]_B[31]_add_9_OUT_cy<5>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<6> (Madd_A[31]_B[31]_add_9_OUT_cy<6>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<7> (Madd_A[31]_B[31]_add_9_OUT_cy<7>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<8> (Madd_A[31]_B[31]_add_9_OUT_cy<8>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<9> (Madd_A[31]_B[31]_add_9_OUT_cy<9>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<10> (Madd_A[31]_B[31]_add_9_OUT_cy<10>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<11> (Madd_A[31]_B[31]_add_9_OUT_cy<11>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<12> (Madd_A[31]_B[31]_add_9_OUT_cy<12>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<13> (Madd_A[31]_B[31]_add_9_OUT_cy<13>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<14> (Madd_A[31]_B[31]_add_9_OUT_cy<14>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<15> (Madd_A[31]_B[31]_add_9_OUT_cy<15>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<16> (Madd_A[31]_B[31]_add_9_OUT_cy<16>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<17> (Madd_A[31]_B[31]_add_9_OUT_cy<17>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<18> (Madd_A[31]_B[31]_add_9_OUT_cy<18>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<19> (Madd_A[31]_B[31]_add_9_OUT_cy<19>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<20> (Madd_A[31]_B[31]_add_9_OUT_cy<20>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<21> (Madd_A[31]_B[31]_add_9_OUT_cy<21>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<22> (Madd_A[31]_B[31]_add_9_OUT_cy<22>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<23> (Madd_A[31]_B[31]_add_9_OUT_cy<23>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<24> (Madd_A[31]_B[31]_add_9_OUT_cy<24>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<25> (Madd_A[31]_B[31]_add_9_OUT_cy<25>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<26> (Madd_A[31]_B[31]_add_9_OUT_cy<26>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<27> (Madd_A[31]_B[31]_add_9_OUT_cy<27>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<28> (Madd_A[31]_B[31]_add_9_OUT_cy<28>)
     MUXCY:CI->O           1   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<29> (Madd_A[31]_B[31]_add_9_OUT_cy<29>)
     MUXCY:CI->O           0   0.023   0.000  Madd_A[31]_B[31]_add_9_OUT_cy<30> (Madd_A[31]_B[31]_add_9_OUT_cy<30>)
     XORCY:CI->O           1   0.370   0.683  Madd_A[31]_B[31]_add_9_OUT_xor<31> (A[31]_B[31]_add_9_OUT<31>)
     LUT6:I1->O            1   0.097   0.295  Mmux_Res[31]_A[31]_MUX_70_o22 (Mmux_Res[31]_A[31]_MUX_70_o21)
     LUT4:I3->O            1   0.097   0.000  Mmux_Res[31]_A[31]_MUX_70_o23 (Res[31]_A[31]_MUX_70_o)
     LD:D                     -0.028          Res_31
    ----------------------------------------
    Total                      3.091ns (1.705ns logic, 1.386ns route)
                                       (55.2% logic, 44.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'ALUop[3]_ALUop[3]_OR_71_o'
  Total number of paths / destination ports: 32 / 32
-------------------------------------------------------------------------
Offset:              0.751ns (Levels of Logic = 1)
  Source:            Res_31 (LATCH)
  Destination:       Res<31> (PAD)
  Source Clock:      ALUop[3]_ALUop[3]_OR_71_o falling

  Data Path: Res_31 to Res<31>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.472   0.279  Res_31 (Res_31)
     OBUF:I->O                 0.000          Res_31_OBUF (Res<31>)
    ----------------------------------------
    Total                      0.751ns (0.472ns logic, 0.279ns route)
                                       (62.8% logic, 37.2% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 64 / 1
-------------------------------------------------------------------------
Delay:               1.912ns (Levels of Logic = 14)
  Source:            A<0> (PAD)
  Destination:       Zero (PAD)

  Data Path: A<0> to Zero
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             7   0.001   0.721  A_0_IBUF (A_0_IBUF)
     LUT6:I0->O            1   0.097   0.000  Mcompar_Zero_lut<0> (Mcompar_Zero_lut<0>)
     MUXCY:S->O            1   0.353   0.000  Mcompar_Zero_cy<0> (Mcompar_Zero_cy<0>)
     MUXCY:CI->O           1   0.023   0.000  Mcompar_Zero_cy<1> (Mcompar_Zero_cy<1>)
     MUXCY:CI->O           1   0.023   0.000  Mcompar_Zero_cy<2> (Mcompar_Zero_cy<2>)
     MUXCY:CI->O           1   0.023   0.000  Mcompar_Zero_cy<3> (Mcompar_Zero_cy<3>)
     MUXCY:CI->O           1   0.023   0.000  Mcompar_Zero_cy<4> (Mcompar_Zero_cy<4>)
     MUXCY:CI->O           1   0.023   0.000  Mcompar_Zero_cy<5> (Mcompar_Zero_cy<5>)
     MUXCY:CI->O           1   0.023   0.000  Mcompar_Zero_cy<6> (Mcompar_Zero_cy<6>)
     MUXCY:CI->O           1   0.023   0.000  Mcompar_Zero_cy<7> (Mcompar_Zero_cy<7>)
     MUXCY:CI->O           1   0.023   0.000  Mcompar_Zero_cy<8> (Mcompar_Zero_cy<8>)
     MUXCY:CI->O           1   0.023   0.000  Mcompar_Zero_cy<9> (Mcompar_Zero_cy<9>)
     MUXCY:CI->O           1   0.253   0.279  Mcompar_Zero_cy<10> (Zero_OBUF)
     OBUF:I->O                 0.000          Zero_OBUF (Zero)
    ----------------------------------------
    Total                      1.912ns (0.911ns logic, 1.001ns route)
                                       (47.7% logic, 52.3% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

=========================================================================


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.36 secs
 
--> 

Total memory usage is 4692904 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   32 (   0 filtered)
Number of infos    :    0 (   0 filtered)