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Adder.syr
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Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.17 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.17 secs
--> Reading design: Adder.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "Adder.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "Adder"
Output Format : NGC
Target Device : xc7a100t-3-csg324
---- Source Options
Top Module Name : Adder
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 32
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "D:\Last lab\Project_28_3\Adder.vhd" into library work
Parsing entity <Adder>.
Parsing architecture <Behavioral> of entity <adder>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating entity <Adder> (architecture <Behavioral>) from library <work>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <Adder>.
Related source file is "D:\Last lab\Project_28_3\Adder.vhd".
Found 32-bit adder for signal <Output> created at line 16.
Summary:
inferred 1 Adder/Subtractor(s).
Unit <Adder> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 1
32-bit adder : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 1
32-bit adder : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <Adder> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block Adder, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : Adder.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 96
# GND : 1
# LUT2 : 32
# MUXCY : 31
# XORCY : 32
# IO Buffers : 96
# IBUF : 64
# OBUF : 32
Device utilization summary:
---------------------------
Selected Device : 7a100tcsg324-3
Slice Logic Utilization:
Number of Slice LUTs: 32 out of 63400 0%
Number used as Logic: 32 out of 63400 0%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 32
Number with an unused Flip Flop: 32 out of 32 100%
Number with an unused LUT: 0 out of 32 0%
Number of fully used LUT-FF pairs: 0 out of 32 0%
Number of unique control sets: 0
IO Utilization:
Number of IOs: 96
Number of bonded IOBs: 96 out of 210 45%
Specific Feature Utilization:
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 2.170ns
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 1552 / 32
-------------------------------------------------------------------------
Delay: 2.170ns (Levels of Logic = 35)
Source: Input1<0> (PAD)
Destination: Output<31> (PAD)
Data Path: Input1<0> to Output<31>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 0.001 0.379 Input1_0_IBUF (Input1_0_IBUF)
LUT2:I0->O 1 0.097 0.000 Madd_Output_lut<0> (Madd_Output_lut<0>)
MUXCY:S->O 1 0.353 0.000 Madd_Output_cy<0> (Madd_Output_cy<0>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<1> (Madd_Output_cy<1>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<2> (Madd_Output_cy<2>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<3> (Madd_Output_cy<3>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<4> (Madd_Output_cy<4>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<5> (Madd_Output_cy<5>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<6> (Madd_Output_cy<6>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<7> (Madd_Output_cy<7>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<8> (Madd_Output_cy<8>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<9> (Madd_Output_cy<9>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<10> (Madd_Output_cy<10>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<11> (Madd_Output_cy<11>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<12> (Madd_Output_cy<12>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<13> (Madd_Output_cy<13>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<14> (Madd_Output_cy<14>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<15> (Madd_Output_cy<15>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<16> (Madd_Output_cy<16>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<17> (Madd_Output_cy<17>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<18> (Madd_Output_cy<18>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<19> (Madd_Output_cy<19>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<20> (Madd_Output_cy<20>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<21> (Madd_Output_cy<21>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<22> (Madd_Output_cy<22>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<23> (Madd_Output_cy<23>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<24> (Madd_Output_cy<24>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<25> (Madd_Output_cy<25>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<26> (Madd_Output_cy<26>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<27> (Madd_Output_cy<27>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<28> (Madd_Output_cy<28>)
MUXCY:CI->O 1 0.023 0.000 Madd_Output_cy<29> (Madd_Output_cy<29>)
MUXCY:CI->O 0 0.023 0.000 Madd_Output_cy<30> (Madd_Output_cy<30>)
XORCY:CI->O 1 0.370 0.279 Madd_Output_xor<31> (Output_31_OBUF)
OBUF:I->O 0.000 Output_31_OBUF (Output<31>)
----------------------------------------
Total 2.170ns (1.511ns logic, 0.659ns route)
(69.6% logic, 30.4% route)
=========================================================================
Cross Clock Domains Report:
--------------------------
=========================================================================
Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 7.88 secs
-->
Total memory usage is 4616872 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)