Control_Unit.syr

Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.06 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.06 secs
 
--> Reading design: Control_Unit.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "Control_Unit.prj"
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "Control_Unit"
Output Format                      : NGC
Target Device                      : xc7a100t-3-csg324

---- Source Options
Top Module Name                    : Control_Unit
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 32
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "D:\Mina\Term 6\Computer Archetcture\Home\Project_22_4\Control_Unit.vhd" into library work
Parsing entity <Control_Unit>.
Parsing architecture <Behavioral> of entity <control_unit>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <Control_Unit> (architecture <Behavioral>) from library <work>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <Control_Unit>.
    Related source file is "D:\Mina\Term 6\Computer Archetcture\Home\Project_22_4\Control_Unit.vhd".
WARNING:Xst:737 - Found 1-bit latch for signal <RegDst>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ALUSrc>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <MemToReg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <RegWhite>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <MemWrite>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Branch>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Summary:
	inferred   6 Latch(s).
	inferred   8 Multiplexer(s).
Unit <Control_Unit> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Latches                                              : 6
 1-bit latch                                           : 6
# Multiplexers                                         : 8
 1-bit 2-to-1 multiplexer                              : 8

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Multiplexers                                         : 8
 1-bit 2-to-1 multiplexer                              : 8

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:3001 - This design contains one or more registers or latches with an active
   asynchronous set and asynchronous reset. While this circuit can be built,
   it creates a sub-optimal implementation in terms of area, power and
   performance. For a more optimal implementation Xilinx highly recommends
   one of the following:

          1) Remove either the set or reset from all registers and latches if
             not needed for required functionality
          2) Modify the code in order to produce a synchronous set
             and/or reset (both is preferred)
          3) Use the -async_to_sync option to transform the asynchronous
             set/reset to synchronous operation
             (timing simulation highly recommended when using this option)

  Please refer to http://www.xilinx.com search string "Artix7 asynchronous set/reset" for more details.

  List of register instances with asynchronous set and reset:
    MemWrite in unit <Control_Unit>
    RegWhite in unit <Control_Unit>
    Branch in unit <Control_Unit>
    MemToReg in unit <Control_Unit>
    ALUSrc in unit <Control_Unit>
    RegDst in unit <Control_Unit>


Optimizing unit <Control_Unit> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block Control_Unit, actual ratio is 0.
Latch RegDst has been replicated 1 time(s) to handle iob=true attribute.
Latch Branch has been replicated 1 time(s) to handle iob=true attribute.
Latch MemToReg has been replicated 1 time(s) to handle iob=true attribute.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : Control_Unit.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 25
#      GND                         : 1
#      LUT3                        : 12
#      LUT4                        : 1
#      LUT5                        : 2
#      LUT6                        : 9
# FlipFlops/Latches                : 9
#      LD                          : 9
# IO Buffers                       : 15
#      IBUF                        : 6
#      OBUF                        : 9

Device utilization summary:
---------------------------

Selected Device : 7a100tcsg324-3 


Slice Logic Utilization: 
 Number of Slice LUTs:                   24  out of  63400     0%  
    Number used as Logic:                24  out of  63400     0%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:     24
   Number with an unused Flip Flop:      24  out of     24   100%  
   Number with an unused LUT:             0  out of     24     0%  
   Number of fully used LUT-FF pairs:     0  out of     24     0%  
   Number of unique control sets:         6

IO Utilization: 
 Number of IOs:                          15
 Number of bonded IOBs:                  15  out of    210     7%  
    IOB Flip Flops/Latches:               9

Specific Feature Utilization:

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
RegDst_G(RegDst_G:O)               | NONE(*)(RegDst)        | 2     |
ALUSrc_G(ALUSrc_G:O)               | NONE(*)(ALUSrc)        | 1     |
MemToReg_G(MemToReg_G:O)           | NONE(*)(MemToReg)      | 2     |
Branch_G(Branch_G:O)               | NONE(*)(Branch)        | 2     |
RegWhite_G(RegWhite_G:O)           | NONE(*)(RegWhite)      | 1     |
MemWrite_G(MemWrite_G:O)           | NONE(*)(MemWrite)      | 1     |
-----------------------------------+------------------------+-------+
(*) These 6 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: No path found
   Minimum input arrival time before clock: 2.103ns
   Maximum output required time after clock: 0.751ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'RegDst_G'
  Total number of paths / destination ports: 24 / 2
-------------------------------------------------------------------------
Offset:              1.450ns (Levels of Logic = 3)
  Source:            Op<1> (PAD)
  Destination:       RegDst (LATCH)
  Destination Clock: RegDst_G falling

  Data Path: Op<1> to RegDst
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            11   0.001   0.740  Op_1_IBUF (Op_1_IBUF)
     LUT6:I0->O            2   0.097   0.515  GND_3_o_GND_3_o_AND_2_o1 (GND_3_o_GND_3_o_AND_2_o)
     LUT3:I0->O            2   0.097   0.000  RegDst_D (RegDst_D)
     LD:D                     -0.028          RegDst
    ----------------------------------------
    Total                      1.450ns (0.195ns logic, 1.255ns route)
                                       (13.4% logic, 86.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'ALUSrc_G'
  Total number of paths / destination ports: 10 / 1
-------------------------------------------------------------------------
Offset:              1.446ns (Levels of Logic = 3)
  Source:            Op<2> (PAD)
  Destination:       ALUSrc (LATCH)
  Destination Clock: ALUSrc_G falling

  Data Path: Op<2> to ALUSrc
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            11   0.001   0.730  Op_2_IBUF (Op_2_IBUF)
     LUT5:I0->O            3   0.097   0.521  GND_3_o_GND_3_o_AND_7_o21 (GND_3_o_GND_3_o_AND_7_o2)
     LUT3:I0->O            1   0.097   0.000  ALUSrc_D (ALUSrc_D)
     LD:D                     -0.028          ALUSrc
    ----------------------------------------
    Total                      1.446ns (0.195ns logic, 1.251ns route)
                                       (13.5% logic, 86.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'MemToReg_G'
  Total number of paths / destination ports: 24 / 2
-------------------------------------------------------------------------
Offset:              1.450ns (Levels of Logic = 3)
  Source:            Op<1> (PAD)
  Destination:       MemToReg (LATCH)
  Destination Clock: MemToReg_G falling

  Data Path: Op<1> to MemToReg
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            11   0.001   0.740  Op_1_IBUF (Op_1_IBUF)
     LUT6:I0->O            2   0.097   0.515  GND_3_o_GND_3_o_AND_6_o1 (GND_3_o_GND_3_o_AND_6_o)
     LUT3:I0->O            2   0.097   0.000  MemToReg_D (MemToReg_D)
     LD:D                     -0.028          MemToReg
    ----------------------------------------
    Total                      1.450ns (0.195ns logic, 1.255ns route)
                                       (13.4% logic, 86.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Branch_G'
  Total number of paths / destination ports: 24 / 2
-------------------------------------------------------------------------
Offset:              1.450ns (Levels of Logic = 3)
  Source:            Op<3> (PAD)
  Destination:       Branch (LATCH)
  Destination Clock: Branch_G falling

  Data Path: Op<3> to Branch
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            11   0.001   0.740  Op_3_IBUF (Op_3_IBUF)
     LUT6:I0->O            2   0.097   0.515  GND_3_o_PWR_3_o_AND_14_o1 (GND_3_o_PWR_3_o_AND_14_o)
     LUT3:I0->O            2   0.097   0.000  Branch_D (Branch_D)
     LD:D                     -0.028          Branch
    ----------------------------------------
    Total                      1.450ns (0.195ns logic, 1.255ns route)
                                       (13.4% logic, 86.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'RegWhite_G'
  Total number of paths / destination ports: 18 / 1
-------------------------------------------------------------------------
Offset:              2.103ns (Levels of Logic = 4)
  Source:            Op<4> (PAD)
  Destination:       RegWhite (LATCH)
  Destination Clock: RegWhite_G falling

  Data Path: Op<4> to RegWhite
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            11   0.001   0.730  Op_4_IBUF (Op_4_IBUF)
     LUT5:I0->O            3   0.097   0.566  GND_3_o_GND_3_o_AND_7_o11 (GND_3_o_GND_3_o_AND_7_o1)
     LUT4:I0->O            2   0.097   0.515  GND_3_o_GND_3_o_AND_8_o1 (GND_3_o_GND_3_o_AND_8_o)
     LUT3:I0->O            1   0.097   0.000  RegWhite_D (RegWhite_D)
     LD:D                     -0.028          RegWhite
    ----------------------------------------
    Total                      2.103ns (0.292ns logic, 1.811ns route)
                                       (13.9% logic, 86.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'MemWrite_G'
  Total number of paths / destination ports: 12 / 1
-------------------------------------------------------------------------
Offset:              1.450ns (Levels of Logic = 3)
  Source:            Op<2> (PAD)
  Destination:       MemWrite (LATCH)
  Destination Clock: MemWrite_G falling

  Data Path: Op<2> to MemWrite
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            11   0.001   0.740  Op_2_IBUF (Op_2_IBUF)
     LUT6:I0->O            2   0.097   0.515  GND_3_o_GND_3_o_AND_12_o1 (GND_3_o_GND_3_o_AND_12_o)
     LUT3:I0->O            1   0.097   0.000  MemWrite_D (MemWrite_D)
     LD:D                     -0.028          MemWrite
    ----------------------------------------
    Total                      1.450ns (0.195ns logic, 1.255ns route)
                                       (13.4% logic, 86.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'RegDst_G'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              0.751ns (Levels of Logic = 1)
  Source:            RegDst_1 (LATCH)
  Destination:       ALUOp<1> (PAD)
  Source Clock:      RegDst_G falling

  Data Path: RegDst_1 to ALUOp<1>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.472   0.279  RegDst_1 (RegDst_1)
     OBUF:I->O                 0.000          ALUOp_1_OBUF (ALUOp<1>)
    ----------------------------------------
    Total                      0.751ns (0.472ns logic, 0.279ns route)
                                       (62.8% logic, 37.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Branch_G'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              0.751ns (Levels of Logic = 1)
  Source:            Branch_1 (LATCH)
  Destination:       ALUOp<0> (PAD)
  Source Clock:      Branch_G falling

  Data Path: Branch_1 to ALUOp<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.472   0.279  Branch_1 (Branch_1)
     OBUF:I->O                 0.000          ALUOp_0_OBUF (ALUOp<0>)
    ----------------------------------------
    Total                      0.751ns (0.472ns logic, 0.279ns route)
                                       (62.8% logic, 37.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'ALUSrc_G'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              0.751ns (Levels of Logic = 1)
  Source:            ALUSrc (LATCH)
  Destination:       ALUSrc (PAD)
  Source Clock:      ALUSrc_G falling

  Data Path: ALUSrc to ALUSrc
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.472   0.279  ALUSrc (ALUSrc_OBUF)
     OBUF:I->O                 0.000          ALUSrc_OBUF (ALUSrc)
    ----------------------------------------
    Total                      0.751ns (0.472ns logic, 0.279ns route)
                                       (62.8% logic, 37.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MemToReg_G'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              0.751ns (Levels of Logic = 1)
  Source:            MemToReg_1 (LATCH)
  Destination:       MemToReg (PAD)
  Source Clock:      MemToReg_G falling

  Data Path: MemToReg_1 to MemToReg
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.472   0.279  MemToReg_1 (MemToReg_1)
     OBUF:I->O                 0.000          MemToReg_OBUF (MemToReg)
    ----------------------------------------
    Total                      0.751ns (0.472ns logic, 0.279ns route)
                                       (62.8% logic, 37.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'RegWhite_G'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              0.751ns (Levels of Logic = 1)
  Source:            RegWhite (LATCH)
  Destination:       RegWhite (PAD)
  Source Clock:      RegWhite_G falling

  Data Path: RegWhite to RegWhite
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.472   0.279  RegWhite (RegWhite_OBUF)
     OBUF:I->O                 0.000          RegWhite_OBUF (RegWhite)
    ----------------------------------------
    Total                      0.751ns (0.472ns logic, 0.279ns route)
                                       (62.8% logic, 37.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MemWrite_G'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              0.751ns (Levels of Logic = 1)
  Source:            MemWrite (LATCH)
  Destination:       MemWrite (PAD)
  Source Clock:      MemWrite_G falling

  Data Path: MemWrite to MemWrite
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.472   0.279  MemWrite (MemWrite_OBUF)
     OBUF:I->O                 0.000          MemWrite_OBUF (MemWrite)
    ----------------------------------------
    Total                      0.751ns (0.472ns logic, 0.279ns route)
                                       (62.8% logic, 37.2% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

=========================================================================


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.24 secs
 
--> 

Total memory usage is 4690784 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    7 (   0 filtered)
Number of infos    :    1 (   0 filtered)