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NetFPGA-PLUS.html
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---
layout: page
---
<h1>NetFPGA PLUS</h1>
<br>
<div id="accordion-PLUS1" class="accordion">
<div class="" data-toggle="collapse" href="#collapse-PLUS1">
<button class="card-title" ><h2>Details  </h2></button>
</div>
<div id="collapse-PLUS1" class="collapse show" data-parent="#accordion-PLUS1">
<p>The NetFPGA PLUS is a code base built for the Xilinx Alveo Data Center Accelerator Card based upon Xilinx Virtex Ultrascale+ FPGAs. The code base currently operates on the U200, U250 and U280 as well as the discontinued <a href="https://www.xilinx.com/products/boards-and-kits/vcu1525-a.html">VCU1525 Acceleration Development Kit.</a></p>
<br>
<p>A typical Alveo board is an FPGA-based PCI Express board with I/O capabilities for 10 and 100 Gbps operation, an x16 gen3 PCIe adapter card. It can be used as NIC, multiport switch, firewall, test/mesaurement environment, and more.</p>
<p>Full feature lists are available at the <a href="https://www.xilinx.com/products/boards-and-kits/alveo.html">Xilinx Alveo website</a>.</p>
<p>Example feaures (e.g., U250)</p>
<ul>
<li>Field Programmable Gate Array</li>
<ul>
<li>Xilinx Ultrascale+ VCU250</li>
<li>1,728K logic cells</li>
<li>57MB block RAM</li>
<li>Fully programmable by the user</li>
</ul>
<li>100-Gigabit Ethernet networking ports</li>
<ul>
<li>Connector bloack on left of PCB interfaces to 2 QSFP+ ports</li>
<li>Directly connected to the FPGA.</li>
<li>Wire-speed processing on all ports at all time using FPGA logic.</li>
</ul>
<li>Double-Data Rate Random Access Memory (DDR4 DRAM)</li>
<ul>
<li>4x 16GB 72b DIMM DDR4</li>
<li>933MHz clock (2400MT/s)</li>
<li>77 GB/s peak memory throughput</li>
</ul>
<li>PCI Express Gen. 3</li>
<ul>
<li>Third generation PCI Express interface, 8Gbps/lane</li>
<li>16 lanes (x16)</li>
<li>Hard IP</li>
<li>Provides CPU access to memory-mapped registers and memory on the NetFPGA hardware</li>
</ul>
<li>Storage</li>
<ul>
<li>FLASH devices</li>
</ul>
<li>Standard PCIe Form Factor</li>
<ul>
<li>Standard PCIe card</li>
<li>3/4 or Full length, full height</li>
</ul>
<li>Flexible, Open-source code</li>
</ul>
</div>
</div>
<br>
<hr>
<div id="accordion-PLUS2" class="accordion">
<div class="collapsed" data-toggle="collapse" href="#collapse-PLUS2">
<button class="card-title" ><h2>Downloads  </h2></button>
</div>
<div id="collapse-PLUS2" class="collapse" data-parent="#accordion-PLUS2">
<h3>Reference Projects</h3>
<table class="downloads">
<tr>
<th>Title</th>
<th>Organisation</th>
<th>Documentation</th>
</tr>
<tr>
<td>Reference Switch</td>
<td>University of Cambridge</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-PLUS/wiki/Reference-Switch" >Wiki</a></td>
</tr>
<tr>
<td>Reference Switch Lite</td>
<td>University of Cambridge</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-PLUS/wiki/Reference-Switch-Lite" >Wiki</a></td>
</tr>
<tr>
<td>Reference NIC</td>
<td>University of Cambridge</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-PLUS/wiki/Reference-NIC" >Wiki</a></td>
</tr>
<tr>
<td>Reference Router</td>
<td>University of Cambridge</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-PLUS/wiki/Reference-Router" >Wiki</a></td>
</tr>
</table>
</div>
</div>
<br>
<hr>
<div id="accordion-PLUS4" class="accordion">
<div class="collapsed" data-toggle="collapse" href="#collapse-PLUS4">
<button class="card-title" ><h2>Resources  </h2></button>
</div>
<div id="collapse-PLUS4" class="collapse" data-parent="#accordion-PLUS4">
<br>
<p class="FAQ">Where can I buy a NetFPGA PLUS Platform?</p>
<ul>
<li>NetFPGA PLUS is initended to run on a range of the Xilinx
Vivado Ultra+ so contact your Xilinx reseller.</li>
</ul>
<p class="FAQ">It seems that my board is broken, what should I do?</p>
<ul>
<li>The Xilinx / Alveo boards have support for hardware repair
andreplacement, contact your Xilinx seller. </li>
</ul>
<p class="FAQ">What if I have Hardware problems with my board?</p>
<ul>
<li>The Xilinx / Alveo boards are no longer bespoke; like any
commodity, consult the people who sold it to you.</li>
</ul>
<p class="FAQ">What if I have Software problems with my board?</p>
<ul>
<li>If the software problem is exclusively related to the
NetFPGA-PLUS codebase, then use the bug-tracking mechaisms on the GitHub
platform associated with the NetFPGA-PLUS repository. </li>
</ul>
<p class="FAQ">How can I get involved with the NetFPGA project?</p>
<ul>
<li>We have a number of mailing lists, unlike SUME, and other previous
boards we no longer require explcit registation. Standby for detals
once we have our new procedures for contribution in place. In the firsst
insntance the issues tracker associated with the PLUS repository is a
great place to start.</li>
<li>Become a <a href="http://www.facebook.com/home.php#/pages/NetFPGA/29922917839" >fan on Facebook</a>.</li>
<li>Become a <a href="https://twitter.com/netfpga" >fan on twitter</a>.</li>
</ul>
<p class="FAQ">How can I obtain the gateware and software package?</p>
<ul>
<li>Check out the repository link in the Resources tab.</li>
</ul>
<p>Once you have used the NetFPGA, we hope that you will contribute to the project.</p>
<p>You can find our Wiki <a href="https://github.com/NetFPGA/netfpga/wiki" >here</a>.</p>
</div>
</div>
<br>
<hr>