Getting Started

[OpenRealTimeSimulation]

To get started with the ORTiS Solver Codegen tools to generate electrical system solvers in C++ for simulation, we recommend to use the precompiled Command Line Interface (CLI) tool under Releases found here:
https://github.com/OpenRealTimeSimulation/SolverCodegen/releases

The CLI tool comes with a user guide which explains in detail how to use the tool and the generated solver code produced by the tool. Electrical components supported by the tools is listed in the guide. The current user guide for v0.9 of the tools is attached here for convenience:
ortis_codegen_cli_guide-0.9.pdf

In Summary

1. You write a netlist file describing the electrical system you wish to simulate, following the syntax supported by the Solver Codegen tools
2. Then, call the CLI tool from the command prompt, passing the netlist file to the tool
3. The CLI tool will then generate a C++ function template for the solver of the electrical system described in your netlist
4. With the solver function template, you can run an offline simulation of the electrical system within a custom C++ testbench or from a simulation tool such as Mathworks Matlab/Simulink, Gnu Octave, Plexim PLECS, or many others that support C++ code.
5. For real-time simulation, the solver C++ function templates can be compiled into executables for real-time CPUs, or high level synthesized into HDL cores for FPGA execution (Xilinx Vivado HLS).

To find more information about the tools, its capabilities, and the applied solver algorithm (LB-LMC), please see the academic paper links listed in the project's readme file found on the repo page. For convenience, here is the link to the free SoftwareX journal paper on the tools, open-access to all: https://www.sciencedirect.com/science/article/pii/S2352711021000054

If you need references for C++, commercial simulators, and FPGA tools, see these third-party links:

• C++ References
• Simulink documentation
• PLECS documentation
• GNU Octave documentation
• Xilinx Vivado high level synthesis documentation

[OpenRealTimeSimulation]

FPGA High Level Synthesis (HLS) Summary

To get a better understanding on how to use Xilinx Vivado HLS to create HDL code or IP cores from C++ function definitions, including the solvers generated by ORTiS solver codegen tool, It is recommended to look at the Vivado HLS user guide (UG902). Here is a link to the guide on Xilinx website, for version 2019.2:

https://docs.xilinx.com/v/u/2019.2-English/ug902-vivado-high-level-synthesis

The UG902 guide provides examples and detailed information for HLS'ing top-level functions in general. This guide can also help you to understand how to HLS the solver functions into IP cores for use in Vivado.

In general, Vivado HLS converts your C or C++ function code definitions into IP cores, or HDL code definitions, which you can deploy into FPGA designs you write within regular (RTL) Vivado. To use the HLS tool, you first write a non-template function that will serve as your top-level definition for the IP core you wish to create for FPGA deployment, such as a simulation solver core for instance. The arguments and return value of the function act as input/output signal ports of the resultant IP core. For the solver functions generated by the ORTiS solver codegen tool, these solver functions are wrapped by a top-level function since the solver functions are generally defined as function templates which cannot be top-level in Vivado HLS.

Then, you test the functionality of your top-level function using a C or C++ testbench of your creation. The testbench will usually provide inputs (stimulus) to the function and record the outputs (response) to either memory or file. It may even compare the outputs to "golden data" to confirm the function is working correctly. For the solvers generated by ORTiS solver codegen tool, the testbench effectively runs a circuit simulation with the solver function, calling it within a loop where each iteration corresponds to a single simulation time step. Besides a custom C or C++ testbench, you can also run testing by calling the top-level function from commercial tools such as Mathworks Simulink/Matlab, Plexim PLECS, or Xilinx suites.

After providing HLS directives (with pragmas inline with C/C++ code or in HLS project settings) which specify the resource usage, timing, scheduling (latency and II), and I/O protocols of the resultant IP core that will be synthesized by the HLS tool (see codegen tool user guide and Vivado HLS guide), you run high level synthesis on the top-level function. This synthesis step will generate VHDL and Verilog definitions of the IP core version of the top-level function, following the HLS directives. Synthesis may also create any Vivado TCL scripts for instancing any internal IP cores the top-level may require (such as a floating-point math unit for instance if using floating point). At this stage, you could copy the generated HDL code and scripts over to a regular RTL Vivado project to use the IP core in a FPGA design. However, depending on complexity of the IP core, you may want to perform other tests or export the IP core into a package that can be used in Vivado's IP integrator or block design approach.

The next step you can take is optional but can be useful: running C(++)/RTL cosimulation. This step reruns your C/C++ testbench, but instead of calling the C/C++ function definition of your top-level, it instead calls the generated HDL code of your top-level which is run in the Xilinx RTL simulator in step with the C/C++ testbench. In this step, Vivado HLS runs the testbench twice, once in pure C/C++ and a second time with C/C++ plus RTL code. With cosimulation, you can verify the synthesized HDL code gives comparable or matching results to the C/C++ version of the top-level. Cosimulation can be slow, depending on top-level complexity, so consider that when testing the HDL code behavior.

The last (and also optional but recommended) step is to export the RTL HDL code of the top-level for IP integration within Vivado. This step produces a Vivado RTL project around the HDL code of the top-level function and with the project generates an IP core package that can be used in block designs of other Vivado projects. This step can also perform out-of-context low-level synthesis and place-and-route (implementation) to get more exact indications of the resource usage and timing of the IP core than what is estimated during the HLS report.

That is the summary of using HLS to create FPGA IP cores from C/C++ functions.