FAC-V: An FPGA-Based AES Coprocessor for RISC-V

This project is an old thesis 2022 project dump and may require additional setup.

Check project publications:

• http://dx.doi.org/10.3390/jlpea12040050
• http://dx.doi.org/10.3390/jlpea12040050

Overview

FAC-V is a project that demonstrates an FPGA-based AES (Advanced Encryption Standard) coprocessor designed for RISC-V processors. The project highlights how FPGA technology can be used to enhance the performance and security of IoT devices through hardware acceleration. This coprocessor can be implemented using both tightly and loosely coupled approaches, offering flexibility and significant performance improvements over software-only solutions.

Features

• Hardware-accelerated AES encryption: Supports AES-128, AES-192, and AES-256.
• Tightly and loosely coupled implementations: Compatible with RISC-V Rocket Core.
• Low power consumption: Designed for low-end IoT devices.
• Easy integration: User-friendly API for seamless integration with various IoT operating systems or baremetal applications.

Quick Start

Prerequisites

• RISC-V toolchain
• FPGA development environment (e.g., Xilinx Vivado)
• Verilog/VHDL knowledge
• Basic understanding of cryptographic algorithms (AES)
• RIOT OS work enviroment
• 2 development boards (Arty, STM)

Usage

Refer to the provided documentation and example code within the repository to understand how to use the FAC-V coprocessor in your projects. The API provided facilitates easy interaction with the coprocessor for encryption and decryption tasks.

Contact

This project is a quick old project dump. If you have any questions or need further information, feel free to contact me.

• Pedro Sousa
• Email: pedro.sousa.pte@outlook.com