ISA-based refactor to move OST1 into a submodule

.gitignore

@@ -7,29 +7,6 @@
 build/*
 !build/.keep
 
-# Ignore generated logs from back-end
-# Good for 10 levels of hierarchy
-piton/design/*/synopsys/*
-!piton/design/*/synopsys/script
-piton/design/*/*/synopsys/*
-!piton/design/*/*/synopsys/script
-piton/design/*/*/*/synopsys/*
-!piton/design/*/*/*/synopsys/script
-piton/design/*/*/*/*/synopsys/*
-!piton/design/*/*/*/*/synopsys/script
-piton/design/*/*/*/*/*/synopsys/*
-!piton/design/*/*/*/*/*/synopsys/script
-piton/design/*/*/*/*/*/*/synopsys/*
-!piton/design/*/*/*/*/*/*/synopsys/script
-piton/design/*/*/*/*/*/*/*/synopsys/*
-!piton/design/*/*/*/*/*/*/*/synopsys/script
-piton/design/*/*/*/*/*/*/*/*/synopsys/*
-!piton/design/*/*/*/*/*/*/*/*/synopsys/script
-piton/design/*/*/*/*/*/*/*/*/*/synopsys/*
-!piton/design/*/*/*/*/*/*/*/*/*/synopsys/script
-piton/design/*/*/*/*/*/*/*/*/*/*/synopsys/*
-!piton/design/*/*/*/*/*/*/*/*/*/*/synopsys/script
-
 # IP for FPGA designs is generated in palce
 # where .xci file is located, so need to ignore
 # these generated files.

.gitmodules

@@ -7,3 +7,9 @@
 [submodule "piton/design/chipset/rv64_platform/bootrom/u-boot/uboot"]
 	path = piton/design/chipset/rv64_platform/bootrom/u-boot/uboot
 	url = git@github.com:u-boot/u-boot.git
+[submodule "piton/verif/diag/sparcv9"]
+    path = piton/verif/diag/sparcv9
+    url = git@github.com:openpiton/sparcv9-ost1-tests.git
+[submodule "piton/design/chip/tile/sparc"]
+    path = piton/design/chip/tile/sparc
+    url = git@github.com:openpiton/ost1-core.git

piton/design/chip/jtag/rtl/jtag_interface_tap.v

@@ -22,7 +22,6 @@
 /////////////////////////////////////////////////////////////////////////
 // Global header file includes
 ////////////////////////////////////////////////////////////////////////
-`include "sys.h"
 // `include "ctu.h"
 `include "jtag.vh"
 

piton/design/chip/rtl/chip.v.pyv

@@ -1,26 +1,27 @@
-// Modified by Princeton University on June 9th, 2015
-// ========== Copyright Header Begin ==========================================
+// Copyright (c) 2015 Princeton University
+// All rights reserved.
 //
-// OpenSPARC T1 Processor File: iop.v
-// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
-// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     * Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in the
+//       documentation and/or other materials provided with the distribution.
+//     * Neither the name of Princeton University nor the
+//       names of its contributors may be used to endorse or promote products
+//       derived from this software without specific prior written permission.
 //
-// The above named program is free software; you can redistribute it and/or
-// modify it under the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// The above named program is distributed in the hope that it will be
-// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-// General Public License for more details.
-//
-// You should have received a copy of the GNU General Public
-// License along with this work; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
-//
-// ========== Copyright Header End ============================================
-
-`ifndef USE_TEST_TOP // useless for older TOPs
+// THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY
+// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 `include "define.tmp.h"
 `include "piton_system.vh"
@@ -1181,5 +1182,3 @@ module chip(
             # print "`endif"
 %>
 endmodule
-
-`endif

piton/design/chip/tile/common/rtl/Flist.clib_common

@@ -20,5 +20,3 @@
 // 
 // ========== Copyright Header End ============================================
 -v swrvr_clib.v
--v u1.beh.v
--v m1.beh.v

piton/design/chip/tile/common/rtl/Flist.dft_common

@@ -19,16 +19,4 @@
 // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 // 
 // ========== Copyright Header End ============================================
--v cluster_header.v
--v cluster_header_sync.v
--v cluster_header_dup.v
--v cluster_header_ctu.v
-//-v ../../analog/bw_clk/rtl/bw_clk_cclk_sync.v
-//-v ../../analog/bw_clk/rtl/bw_clk_cclk_scanlasr_2x.v
-//-v dftlib.v
-//-v test_stub_bist.v
-//-v test_stub_scan.v
--v synchronizer_asr.v
--v synchronizer_asr_dup.v
--v sync_pulse_synchronizer.v
--v clk_gating_latch.v
+-v clk_gating_latch.v

piton/design/chip/tile/common/rtl/Flist.ucb_common

@@ -21,6 +21,3 @@
 // ========== Copyright Header End ============================================
 -v ucb_bus_in.v
 -v ucb_bus_out.v
--v ucb_flow_2buf.v
--v ucb_flow_spi.v
--v ucb_noflow.v