diff --git a/piton/design/chip/tile/l15/rtl/Flist.l15 b/piton/design/chip/tile/l15/rtl/Flist.l15 index 7d151fb3b..940c99009 100644 --- a/piton/design/chip/tile/l15/rtl/Flist.l15 +++ b/piton/design/chip/tile/l15/rtl/Flist.l15 @@ -31,7 +31,6 @@ l15_mshr.v l15_pipeline.v rf_l15_lruarray.v rf_l15_mesi.v -rf_l15_lrsc_flag.v rf_l15_wmt.v l15_cpxencoder.v diff --git a/piton/design/chip/tile/l15/rtl/l15.v b/piton/design/chip/tile/l15/rtl/l15.v index e3fb01334..deff7f22d 100644 --- a/piton/design/chip/tile/l15/rtl/l15.v +++ b/piton/design/chip/tile/l15/rtl/l15.v @@ -565,26 +565,6 @@ rf_l15_mesi mesi( .read_data(mesi_l15_dout_s2) ); -// LRSC Flag array -wire l15_lrsc_flag_read_val_s1; -wire [`L15_CACHE_INDEX_WIDTH-1:0] l15_lrsc_flag_read_index_s1; -wire l15_lrsc_flag_write_val_s2; -wire [`L15_CACHE_INDEX_WIDTH-1:0] l15_lrsc_flag_write_index_s2; -wire [3:0] l15_lrsc_flag_write_mask_s2; -wire [3:0] l15_lrsc_flag_write_data_s2; -wire [3:0] lrsc_flag_l15_dout_s2; - -rf_l15_lrsc_flag lrsc_flag( - .clk(clk), - .rst_n(rst_n), - .read_valid(l15_lrsc_flag_read_val_s1), - .read_index(l15_lrsc_flag_read_index_s1), - .write_valid(l15_lrsc_flag_write_val_s2), - .write_index(l15_lrsc_flag_write_index_s2), - .write_mask(l15_lrsc_flag_write_mask_s2), - .write_data(l15_lrsc_flag_write_data_s2), - .read_data(lrsc_flag_l15_dout_s2) -); // // home map table array // wire l15_hmt_read_val_s1; @@ -656,7 +636,6 @@ l15_pipeline pipeline( .dtag_l15_dout_s2(dtag_l15_dout_s2), .dcache_l15_dout_s3(dcache_l15_dout_s3), .mesi_l15_dout_s2(mesi_l15_dout_s2), - .lrsc_flag_l15_dout_s2(lrsc_flag_l15_dout_s2), .lruarray_l15_dout_s2(lruarray_l15_dout_s2), .wmt_l15_data_s3(wmt_l15_data_s3), .pcxdecoder_l15_rqtype (transducer_l15_rqtype), @@ -718,12 +697,6 @@ l15_pipeline pipeline( .l15_mesi_write_index_s2(l15_mesi_write_index_s2), .l15_mesi_write_mask_s2(l15_mesi_write_mask_s2), .l15_mesi_write_data_s2(l15_mesi_write_data_s2), - .l15_lrsc_flag_read_val_s1(l15_lrsc_flag_read_val_s1), - .l15_lrsc_flag_read_index_s1(l15_lrsc_flag_read_index_s1), - .l15_lrsc_flag_write_val_s2(l15_lrsc_flag_write_val_s2), - .l15_lrsc_flag_write_index_s2(l15_lrsc_flag_write_index_s2), - .l15_lrsc_flag_write_mask_s2(l15_lrsc_flag_write_mask_s2), - .l15_lrsc_flag_write_data_s2(l15_lrsc_flag_write_data_s2), .l15_wmt_read_val_s2(l15_wmt_read_val_s2), .l15_wmt_read_index_s2(l15_wmt_read_index_s2), .l15_wmt_write_val_s3(l15_wmt_write_val_s3), diff --git a/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv b/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv index 57f6ebf4a..ffe52e90a 100644 --- a/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv +++ b/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv @@ -126,15 +126,6 @@ module l15_pipeline( output reg [`L15_UNPARAM_7_0] l15_mesi_write_mask_s2, output reg [`L15_UNPARAM_7_0] l15_mesi_write_data_s2, - // lrsc_flag - output reg l15_lrsc_flag_read_val_s1, - output reg [`L15_CACHE_INDEX_WIDTH-1:0] l15_lrsc_flag_read_index_s1, - input wire [`L15_UNPARAM_3_0] lrsc_flag_l15_dout_s2, - output reg l15_lrsc_flag_write_val_s2, - output reg [`L15_CACHE_INDEX_WIDTH-1:0] l15_lrsc_flag_write_index_s2, - output reg [`L15_UNPARAM_3_0] l15_lrsc_flag_write_mask_s2, - output reg [`L15_UNPARAM_3_0] l15_lrsc_flag_write_data_s2, - // lruarray output reg l15_lruarray_read_val_s1, output reg [`L15_CACHE_INDEX_WIDTH-1:0] l15_lruarray_read_index_s1, @@ -2044,8 +2035,20 @@ end //////////////////////////// // LRSC FLAG read control logics //////////////////////////// + +// LRSC flag: read in stage 1; write in the end of stage 2 +reg [`L15_CACHE_INDEX_WIDTH-1:0] l15_lrsc_flag_index; +reg l15_lrsc_flag; +reg [`L15_UNPARAM_1_0] l15_lrsc_flag_way; + + +// Remove decoder_lrsc_flag_read_op_s1 reg lrsc_flag_read_val_s1; reg [`L15_CACHE_INDEX_WIDTH-1:0] lrsc_flag_read_index_s1; +reg l15_lrsc_flag_read_val_s1; +reg l15_lrsc_flag_read_match_s1; +reg l15_lrsc_flag_readout_s2; +reg [`L15_UNPARAM_1_0] l15_lrsc_flag_stored_way_s2; always @ * begin lrsc_flag_read_val_s1 = 0; @@ -2059,7 +2062,27 @@ begin endcase l15_lrsc_flag_read_val_s1 = lrsc_flag_read_val_s1 && val_s1 && !stall_s1; - l15_lrsc_flag_read_index_s1[`L15_CACHE_INDEX_WIDTH-1:0] = lrsc_flag_read_index_s1; + l15_lrsc_flag_read_match_s1 = (lrsc_flag_read_index_s1 == l15_lrsc_flag_index); +end + +always @(posedge clk) +begin + if (!rst_n) + begin + l15_lrsc_flag_readout_s2 <= 1'b0; + end + else + begin + if (l15_lrsc_flag_read_val_s1 && l15_lrsc_flag_read_match_s1) + begin + l15_lrsc_flag_readout_s2 <= l15_lrsc_flag; + l15_lrsc_flag_stored_way_s2 <= l15_lrsc_flag_way; + end + else + begin + l15_lrsc_flag_readout_s2 <= 1'b0; + end + end end //////////////////////////// @@ -2525,11 +2548,7 @@ begin // 2'd2 ? 4'b0100 : // 4'b1000 ; - tagcheck_lrsc_flag_s2 = (tagcheck_val_s2 == 1'b0) ? 1'b0 : - (tagcheck_way_s2 == 2'd0) ? lrsc_flag_l15_dout_s2[0] : - (tagcheck_way_s2 == 2'd1) ? lrsc_flag_l15_dout_s2[1] : - (tagcheck_way_s2 == 2'd2) ? lrsc_flag_l15_dout_s2[2] : - lrsc_flag_l15_dout_s2[3] ; + tagcheck_lrsc_flag_s2 = (tagcheck_way_s2 == l15_lrsc_flag_stored_way_s2) ? l15_lrsc_flag_readout_s2 : 1'b0; tagcheck_state_s2 = (tagcheck_val_s2 == 1'b0) ? `L15_MESI_STATE_I : (tagcheck_way_s2 == 2'd0) ? mesi_state_way0_s2 : @@ -2925,6 +2944,8 @@ reg lrsc_flag_write_val_s2; reg [`L15_CACHE_INDEX_MASK] lrsc_flag_write_index_s2; reg [`L15_UNPARAM_1_0] lrsc_flag_write_way_s2; reg lrsc_flag_write_state_s2; +reg l15_lrsc_flag_write_val_s2; +reg l15_lrsc_flag_write_match_s2; always @ * begin lrsc_flag_write_val_s2 = 0; @@ -2961,15 +2982,32 @@ begin lrsc_flag_write_state_s2 = 1'b0; end endcase - // bugfix (stall signal needs to be here) // trin todo: why stall_s2 is needed l15_lrsc_flag_write_val_s2 = lrsc_flag_write_val_s2 && val_s2 && !stall_s2; - l15_lrsc_flag_write_index_s2[`L15_CACHE_INDEX_MASK] = lrsc_flag_write_index_s2; - l15_lrsc_flag_write_mask_s2[`L15_UNPARAM_3_0] = (lrsc_flag_write_way_s2 == 0) ? 4'b0001 : - (lrsc_flag_write_way_s2 == 1) ? 4'b0010 : - (lrsc_flag_write_way_s2 == 2) ? 4'b0100 : - 4'b1000 ; - l15_lrsc_flag_write_data_s2[`L15_UNPARAM_3_0] = {4{lrsc_flag_write_state_s2}}; + l15_lrsc_flag_write_match_s2 = (lrsc_flag_write_index_s2 == l15_lrsc_flag_index) && + (lrsc_flag_write_way_s2 == l15_lrsc_flag_way); +end + + +always @(posedge clk) +begin + if (!rst_n) + begin + l15_lrsc_flag <= 1'b0; + end + else + begin + if (l15_lrsc_flag_write_val_s2 && lrsc_flag_write_state_s2) + begin + l15_lrsc_flag_index <= lrsc_flag_write_index_s2; // TODO check width + l15_lrsc_flag_way <= lrsc_flag_write_way_s2; + l15_lrsc_flag <= 1'b1; + end + else if (l15_lrsc_flag_write_val_s2 && !lrsc_flag_write_state_s2 && l15_lrsc_flag_write_match_s2) + begin + l15_lrsc_flag <= 1'b0; + end + end end //////////////////////////// diff --git a/piton/design/chip/tile/l15/rtl/rf_l15_lrsc_flag.v.pyv b/piton/design/chip/tile/l15/rtl/rf_l15_lrsc_flag.v.pyv deleted file mode 100644 index b98ac0588..000000000 --- a/piton/design/chip/tile/l15/rtl/rf_l15_lrsc_flag.v.pyv +++ /dev/null @@ -1,126 +0,0 @@ -/* -Copyright (c) 2015 Princeton University -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of Princeton University nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - - -//================================================================================================== -// Filename : rf_l15_lrsc_flag.v -// Created On : 2018-11-08 18:14:58 -// Last Modified : -// Revision : -// Author : Fei Gao -// Company : Princeton University -// Email : feig@princeton.edu -// -// Description : -// -// -//================================================================================================== -//rf_l15_lrsc_flag.v - -//`timescale 1 ns / 10 ps -//`default_nettype none - - -<% - import pyhplib - from pyhplib import * -%> -module rf_l15_lrsc_flag( - input wire clk, - input wire rst_n, - - input wire read_valid, - input wire [`L15_CACHE_INDEX_WIDTH-1:0] read_index, - - input wire write_valid, - input wire [`L15_CACHE_INDEX_WIDTH-1:0] write_index, - input wire [3:0] write_mask, - input wire [3:0] write_data, - - output wire [3:0] read_data - ); - -<% - linesize = 16 - numset = int(CONFIG_L15_SIZE)/int(CONFIG_L15_ASSOCIATIVITY)/linesize -%> - -// reg read_valid_f; -reg [`L15_CACHE_INDEX_WIDTH-1:0] read_index_f; -reg [`L15_CACHE_INDEX_WIDTH-1:0] write_index_f; -reg [3:0] write_data_f; -reg [3:0] write_mask_f; -reg write_valid_f; - -reg [3:0] regfile [0:`L15_CACHE_INDEX_VECTOR_WIDTH-1]; - -always @ (posedge clk) -begin - if (!rst_n) - begin - read_index_f <= 0; - end - else - if (read_valid) - read_index_f <= read_index; - else - read_index_f <= read_index_f; -end - -// read port -assign read_data = regfile[read_index_f]; - -// Write port -always @ (posedge clk) -begin - write_valid_f <= write_valid; - if (write_valid) - begin - write_data_f <= write_data; - write_index_f <= write_index; - write_mask_f <= write_mask; - end -end - -always @ (posedge clk) -begin - if (!rst_n) - begin - <% - for i in range (numset): - print "regfile[%d] <= 4'b0;" % (i) - %> - // regfile <= 1024'b0; - end - else - if (write_valid_f) - begin - // regfile[write_index] <= (write_data & write_mask) | (regfile[write_index] & ~write_mask); - regfile[write_index_f] <= (write_data_f & write_mask_f) | (regfile[write_index_f] & ~write_mask_f); - end -end -endmodule