HIP-CPU for other CPU architectures?

[jdayal-ssi]

Hello,

I have a few questions about HIP-CPU. First, is the intent for HIP-CPU to only support AMD CPUs, or will the project accept upstream efforts to run this on other architectures (ARM, RISC-V, etc)?

Also, what does it use to parallelize? From what I can see, it doesn't use OpenMP, so does it do it all itself with pthreads or something similar? According to this, ROCm can use OpenMP as the "backend" so perhaps this is how HIP-CPU operates?
https://docs.amd.com/en/docs-5.3.0/reference/openmp/openmp.html

Thank you!

[jlgreathouse]

@jdayal-ssi I do not believe we have any issues acceptching patches that attempt to get HIP-CPU working on other CPU architectures. We like AMD CPUs, of course, but the general idea of this repo is to help make HIP usable for everyone.

The current implementation uses Parallel Algorithms component of the C++ STL to implement the parallelization. On GCC for Mac and Linux, this implementation uses TBB under the hood.

[jdayal-ssi]

I do not believe we have any issues acceptching patches that attempt to get HIP-CPU working on other CPU architectures.

This is good to know! I ask a similar question on the HIP github, and they were firm that HIP would only accept patches or changes for AMD related hardware: ROCm/HIP#3263

From perusing the documentation, it also states that ROCm can use OpenMP to parallelize on CPUs and accelerators (via target offload). Are there reasons why HIP-CPU takes a different approach than the ROCm + OpenMP route? Thanks in advance!