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[ROCm] Fixed an issue with InstructionSchedHintsPass
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zoranjovanovic-ns committed Dec 15, 2024
1 parent 2d9229a commit 2bd6f7e
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Showing 3 changed files with 13 additions and 1 deletion.
11 changes: 11 additions & 0 deletions third_party/triton/temporary/fix_InsertInstructionSchedHints.patch
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
--- a/third_party/amd/include/TritonAMDGPUToLLVM/Passes.td
+++ b/third_party/amd/include/TritonAMDGPUToLLVM/Passes.td
@@ -59,7 +59,7 @@
let summary = "Insert instruction scheduling hints after the dot ops in the main loop";
let constructor = "mlir::triton::createInsertInstructionSchedHintsPass()";

- let dependentDialects = ["mlir::LLVM::LLVMDialect"];
+ let dependentDialects = ["mlir::LLVM::LLVMDialect", "mlir::triton::amdgpu::TritonAMDGPUDialect"];
}

def LowerInstructionSchedHints : Pass<"lower-insert-instruction-sched-hints", "mlir::ModuleOp"> {
1 change: 1 addition & 0 deletions third_party/triton/temporary/series.bzl
Original file line number Diff line number Diff line change
Expand Up @@ -17,5 +17,6 @@ temporary_patch_list = [
"//third_party/triton:temporary/fix_left_shift_overflow.patch",
"//third_party/triton:temporary/prefetch.patch",
"//third_party/triton:temporary/i4_to_bf16.patch",
"//third_party/triton:temporary/fix_InsertInstructionSchedHints.patch",
# Add new patches just above this line
]
Original file line number Diff line number Diff line change
Expand Up @@ -91,7 +91,7 @@ absl::Status CreateTritonPipeline(
pm.addPass(mlir::createTritonAMDGPUStreamPipelinePass());
pm.addPass(mlir::createCanonicalizerPass());
}
//pm.addPass(mt::createInsertInstructionSchedHintsPass());
pm.addPass(mt::createInsertInstructionSchedHintsPass());
pm.addPass(mt::gpu::createTritonGPUOptimizeDotOperands({true}));
pm.addPass(mt::gpu::createTritonGPURemoveLayoutConversions());
pm.addPass(mt::gpu::createTritonGPUReduceDataDuplication());
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