{"payload":{"header_redesign_enabled":false,"results":[{"id":"462658446","archived":false,"color":"#e34c26","followers":3,"has_funding_file":false,"hl_name":"Rafsan7238/CSE460_Labs","hl_trunc_description":"This repo contains the lab files for my CSE460: VLSI course at BracU, written in VHDL, DHCP and MicroWind. ","language":"HTML","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":462658446,"name":"CSE460_Labs","owner_id":64797072,"owner_login":"Rafsan7238","updated_at":"2022-04-18T17:13:57.959Z","has_issues":true}},"sponsorable":false,"topics":["dhcp","vhdl","hardware-designs","vlsi","bracu","cse460","microwind"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":59,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253ARafsan7238%252FCSE460_Labs%2B%2Blanguage%253AHTML","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/Rafsan7238/CSE460_Labs/star":{"post":"IvCexLrRf7fw7n-slrCxqCJLSyZq3ITUrbu4_PWd5vpa43n_tDPcgCqnt2FRzJ-9qz7rPrV_-7KDygExF6JEag"},"/Rafsan7238/CSE460_Labs/unstar":{"post":"Ms8jSBFcv440zFXa4hv-8yL_h6Ev96a3lB3YJC_-fYO3rKnaCzbAbd5sEd0XiP2rArbWADPBESuhLA3-jqN51w"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"YzrMfatVxqMgd1-q7Iqz-P0mrTgWDWcZivHZT_wTyBzhZZDfM38eoQB4Fr2fzlzWAQpG0Y0IY9atOdI0_ZNIDw"}}},"title":"Repository search results"}