GitHub - SMath0510/CS2310-CS2610-Labs: Contains the codes and reports that were done as a part of the CS2310 and CS2610: Computer Architecture

This is the code for the Verilog Final Assignment.

The way to run this code is to open the terminal in the desired folder where we have stored the verilog files.

In the command prompt/ shell / terminal we type in the command that helps us to compile all the files and generate the a.out file

Command 1: iverilog HalfAdder.v FullAdder.v RCA8.v NOT.v OR.v Subtract.v Add.v AND.v Decrement.v Increment.v Decoder.v CPU.v TestBench.v

The other command helps us in running the a.out file and generates the outputs based on the instructions given

Command 2: vvp a.out

The final command helps us in plotting our results in a graph and this gives a visual repesentation of our program by plotting it in the graph

Command 3: gtkwave CPU.vcd

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
AND.v		AND.v
Add.v		Add.v
CPU.v		CPU.v
Decoder.v		Decoder.v
Decrement.v		Decrement.v
FullAdder.v		FullAdder.v
HalfAdder.v		HalfAdder.v
Increment.v		Increment.v
MUX.v		MUX.v
NOT.v		NOT.v
OR.v		OR.v
RCA8.v		RCA8.v
README.md		README.md
Report.pdf		Report.pdf
Subtract.v		Subtract.v
TestBench.v		TestBench.v