VLSI Enthusiast | Aspiring design verification trainee | TIET '26 | ECE
- From Saharanpur, lives in Patiala
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22:49
(UTC +05:30) - https://github.com/SUHANI102003
- in/suhani-jain-16a6b4323
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FSM-BASED-PROJECTS
FSM-BASED-PROJECTS PublicMini projects based on Finite State Machines (FSM)
Verilog
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