Lab done to create a Single Cycle Processor (SCP)
Created a SCP using Verilog in Intel Quartus Prime.
The .v files in the V files folder hold the different modules (components) of the SCP.
The .vwf files in the VWF Files folder hold the test results from testing the different components and the whole processor. These VWF files are detailed with more explanation in the Write up for the lab pdf in the main directory.
For a quick look at what's going on, look at the first page of the write up pdf. It shows the different components on a SCP diagram. The last few pages also show the tests done to test the entire processor.
The mipsSCP.asm is code written in MARS and it's the code that I converted to instuctions in Verilog to test the SCP's functioning. The mipsSCP.asm file is heavily commented for explanation.