From d0b3c91784dae4cd0aebaeeaeb05e29ee344dcac Mon Sep 17 00:00:00 2001 From: Yindong Date: Mon, 23 Dec 2024 10:38:26 +0800 Subject: [PATCH 1/3] add translation for state retrieve. --- .../LC_MESSAGES/SpinalHDL/Libraries/fsm.po | 198 +++++++++--------- 1 file changed, 98 insertions(+), 100 deletions(-) diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fsm.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fsm.po index 1ab80580fc..406ccaadc3 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fsm.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fsm.po @@ -1,26 +1,24 @@ - msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" -"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" -"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " -"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" -"Type:text/plain; charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" -"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language-Team:LANGUAGE MIME-Version:1.0Content-" -"Type:text/plain; charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-01 11:48+0800PO-" +"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language:" +"zh_CNLanguage-Team:zh_CN Plural-Forms:nplurals=1; plural=0;MIME-" +"Version:1.0Content-Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-Revision-Date:" +"YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; charset=UTF-8\n" "POT-Creation-Date: 2024-12-20 14:15+0000\n" -"PO-Revision-Date: 2024-01-10 17:06+0000\n" +"PO-Revision-Date: 2024-12-23 10:37+0800\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" +"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Language-Team: Chinese (Simplified) \n" -"Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" +"Plural-Forms: nplurals=1; plural=0;\n" "Generated-By: Babel 2.16.0\n" +"X-Generator: Poedit 3.4.4\n" #: ../../SpinalHDL/Libraries/fsm.rst:7 msgid "State machine" @@ -32,10 +30,11 @@ msgstr "简介" #: ../../SpinalHDL/Libraries/fsm.rst:12 msgid "" -"In SpinalHDL you can define your state machine like in VHDL/Verilog, by " -"using enumerations and switch/case statements. But in SpinalHDL you can " -"also use a dedicated syntax." -msgstr "在SpinalHDL中，您可以像在VHDL/Verilog中一样，通过使用枚举和switch/case语句来定义状态机。但在SpinalHDL中，您还可以使用专门的语句。" +"In SpinalHDL you can define your state machine like in VHDL/Verilog, by using enumerations " +"and switch/case statements. But in SpinalHDL you can also use a dedicated syntax." +msgstr "" +"在SpinalHDL中，您可以像在VHDL/Verilog中一样，通过使用枚举和switch/case语句来定义状态机。但在" +"SpinalHDL中，您还可以使用专门的语句。" #: ../../SpinalHDL/Libraries/fsm.rst:14 msgid "The state machine below is implemented in the following examples:" @@ -99,8 +98,8 @@ msgstr "入口点" #: ../../SpinalHDL/Libraries/fsm.rst:121 msgid "" -"A state can be defined as the entry point of the state machine by " -"extending the EntryPoint trait:" +"A state can be defined as the entry point of the state machine by extending the EntryPoint " +"trait:" msgstr "通过扩展EntryPoint特征，可以将状态定义为状态机的入口点：" #: ../../SpinalHDL/Libraries/fsm.rst:127 @@ -113,41 +112,40 @@ msgstr "转换" #: ../../SpinalHDL/Libraries/fsm.rst:137 msgid "" -"Transitions are represented by ``goto(nextState)``, which schedules the " -"state machine to be in ``nextState`` the next cycle." +"Transitions are represented by ``goto(nextState)``, which schedules the state machine to be " +"in ``nextState`` the next cycle." msgstr "转换由 ``goto(nextState)`` 表示，它使状态机的状态在下一个周期转换到 ``nextState`` 。" #: ../../SpinalHDL/Libraries/fsm.rst:138 msgid "" -"``exit()`` schedules the state machine to be in the boot state the next " -"cycle (or, in ``StateFsm``, to exit the current nested state machine)." -msgstr "``exit()`` 使状态机在下一个周期处于启动(boot)状态（或者，在 ``StateFsm`` 中，退出当前的嵌套状态机）。" +"``exit()`` schedules the state machine to be in the boot state the next cycle (or, in " +"``StateFsm``, to exit the current nested state machine)." +msgstr "" +"``exit()`` 使状态机在下一个周期处于启动(boot)状态（或者，在 ``StateFsm`` 中，退出当前的嵌套" +"状态机）。" #: ../../SpinalHDL/Libraries/fsm.rst:140 msgid "" -"These two functions can be used inside state definitions (see below) or " -"using ``always { yourStatements }``, which always applies " -"``yourStatements``, with a priority over states." +"These two functions can be used inside state definitions (see below) or using ``always " +"{ yourStatements }``, which always applies ``yourStatements``, with a priority over states." msgstr "" -"这两个函数可以在状态定义中使用（见下文），或使用 ``always { yourStatements }`` ，这将始终应用 " -"``yourStatements``，并且优先级高于状态。" +"这两个函数可以在状态定义中使用（见下文），或使用 ``always { yourStatements }`` ，这将始终应" +"用 ``yourStatements``，并且优先级高于状态。" #: ../../SpinalHDL/Libraries/fsm.rst:144 msgid "State encoding" msgstr "状态编码" #: ../../SpinalHDL/Libraries/fsm.rst:146 -#, fuzzy msgid "" -"By default the FSM state vector will be encoded using the native encoding" -" of the language/tools the RTL is generated for (Verilog or VHDL). This " -"default can be overridden by using the ``setEncoding(...)`` method which " -"either takes a ``SpinalEnumEncoding`` or varargs of type ``(State, " -"BigInt)`` for a custom encoding." +"By default the FSM state vector will be encoded using the native encoding of the language/" +"tools the RTL is generated for (Verilog or VHDL). This default can be overridden by using " +"the ``setEncoding(...)`` method which either takes a ``SpinalEnumEncoding`` or varargs of " +"type ``(State, BigInt)`` for a custom encoding." msgstr "" -"默认情况下，FSM状态向量将使用（针对Verilog或VHDL）生成RTL的语言/工具的本地编码进行编码。可以通过使用 " -"``setEncoding(...)`` 函数覆盖此默认设置，该方法接收 ``SpinalEnumEncoding`` 或类型为 " -"``(State, BigInt)`` 的可变参数以进行自定义编码。" +"默认情况下，FSM 状态向量将使用 RTL 生成语言/工具（Verilog 或 VHDL）的本地编码进行编码。可以" +"使用 ``setEncoding(...)`` 方法重写默认编码，该方法可以使用 ``SpinalEnumEncoding`` 或 " +"``(State,BigInt)`` 类型的 varargs 来获取自定义编码。" #: ../../SpinalHDL/Libraries/fsm.rst:150 msgid "Using a ``SpinalEnumEncoding``" @@ -159,14 +157,13 @@ msgstr "使用自定义编码" #: ../../SpinalHDL/Libraries/fsm.rst:169 msgid "" -"When using the ``graySequential`` enum encoding, no check is done to " -"verify that the FSM transitions only produce single-bit changes in the " -"state vector. The encoding is done according to the order of state " -"definitions and the designer must ensure that only valid transitions are " -"done if needed." +"When using the ``graySequential`` enum encoding, no check is done to verify that the FSM " +"transitions only produce single-bit changes in the state vector. The encoding is done " +"according to the order of state definitions and the designer must ensure that only valid " +"transitions are done if needed." msgstr "" -"当使用 ``graySequential`` " -"枚举编码时，不会进行任何检查以验证FSM转换是否只在状态向量中产生单比特的变化。编码是根据状态定义的顺序完成的，设计者必须确保仅在需要时进行有效的转换。" +"当使用 ``graySequential`` 枚举编码时，不会进行任何检查以验证FSM转换是否只在状态向量中产生单" +"比特的变化。编码是根据状态定义的顺序完成的，设计者必须确保仅在需要时进行有效的转换。" #: ../../SpinalHDL/Libraries/fsm.rst:174 msgid "States" @@ -193,21 +190,21 @@ msgid "``StateParallelFsm``" msgstr "``StateParallelFsm``" #: ../../SpinalHDL/Libraries/fsm.rst:183 -msgid "" -"Each of them provides the following functions to define the logic " -"associated to them:" +msgid "Each of them provides the following functions to define the logic associated to them:" msgstr "它们每个都提供了以下函数来定义与之相关的逻辑：" #: ../../SpinalHDL/Libraries/fsm.rst:196 msgid "" -"``yourStatements`` is applied when the state machine is not in ``state`` " -"and will be in ``state`` the next cycle" -msgstr "当状态机不在 ``state`` 状态，并且在下一个周期将处于 ``state`` 状态时，执行 ``yourStatements``" +"``yourStatements`` is applied when the state machine is not in ``state`` and will be in " +"``state`` the next cycle" +msgstr "" +"当状态机不在 ``state`` 状态，并且在下一个周期将处于 ``state`` 状态时，执行 " +"``yourStatements``" #: ../../SpinalHDL/Libraries/fsm.rst:202 msgid "" -"``yourStatements`` is applied when the state machine is in ``state`` and " -"will be in another state the next cycle" +"``yourStatements`` is applied when the state machine is in ``state`` and will be in another " +"state the next cycle" msgstr "当状态机在 ``state`` 状态时执行 ``yourStatements`` ，并且在下一个周期将处于另一个状态" #: ../../SpinalHDL/Libraries/fsm.rst:208 @@ -216,9 +213,11 @@ msgstr "当状态机在 ``state`` 状态时执行 ``yourStatements``" #: ../../SpinalHDL/Libraries/fsm.rst:214 msgid "" -"``yourStatements`` is executed when the state machine will be in " -"``state`` the next cycle (even if it is already in it)" -msgstr "当状态机在下一个周期处于 ``state`` 状态时， ``yourStatements`` 被执行（即使它已经处于该状态）" +"``yourStatements`` is executed when the state machine will be in ``state`` the next cycle " +"(even if it is already in it)" +msgstr "" +"当状态机在下一个周期处于 ``state`` 状态时， ``yourStatements`` 被执行（即使它已经处于该状" +"态）" #: ../../SpinalHDL/Libraries/fsm.rst:216 msgid "``state.`` is implicit in a ``new State`` block:" @@ -230,12 +229,11 @@ msgstr "StateDelay（状态延迟）" #: ../../SpinalHDL/Libraries/fsm.rst:238 msgid "" -"``StateDelay`` allows you to create a state which waits for a fixed " -"number of cycles before executing statements in ``whenCompleted {...}``. " -"The preferred way to use it is:" +"``StateDelay`` allows you to create a state which waits for a fixed number of cycles before " +"executing statements in ``whenCompleted {...}``. The preferred way to use it is:" msgstr "" -"``StateDelay`` 允许您创建一个状态，该状态在执行 ``whenCompleted {...}`` " -"中的语句之前等待固定数量的周期。首选的使用方式是：" +"``StateDelay`` 允许您创建一个状态，该状态在执行 ``whenCompleted {...}`` 中的语句之前等待固定" +"数量的周期。首选的使用方式是：" #: ../../SpinalHDL/Libraries/fsm.rst:248 msgid "It can also be written in one line:" @@ -247,12 +245,11 @@ msgstr "StateFsm" #: ../../SpinalHDL/Libraries/fsm.rst:257 msgid "" -"``StateFsm`` allows you to describe a state containing a nested state " -"machine. When the nested state machine is done (exited), statements in " -"``whenCompleted { ... }`` are executed." +"``StateFsm`` allows you to describe a state containing a nested state machine. When the " +"nested state machine is done (exited), statements in ``whenCompleted { ... }`` are executed." msgstr "" -"``StateFsm`` 允许您描述一个包含嵌套状态机的状态。当嵌套状态机完成（退出）时，执行 ``whenCompleted { ... }``" -" 中的语句。" +"``StateFsm`` 允许您描述一个包含嵌套状态机的状态。当嵌套状态机完成（退出）时，执行 " +"``whenCompleted { ... }`` 中的语句。" #: ../../SpinalHDL/Libraries/fsm.rst:259 msgid "There is an example of StateFsm definition :" @@ -260,10 +257,11 @@ msgstr "这是一个StateFsm定义的示例：" #: ../../SpinalHDL/Libraries/fsm.rst:290 msgid "" -"In the example above, ``exit()`` makes the state machine jump to the boot" -" state (a internal hidden state). This notifies ``StateFsm`` about the " -"completion of the inner state machine." -msgstr "在上面的示例中， ``exit()`` 使状态机跳转到启动状态（内部隐藏状态）。这将通知 ``StateFsm`` 其内部状态机已经完成。" +"In the example above, ``exit()`` makes the state machine jump to the boot state (a internal " +"hidden state). This notifies ``StateFsm`` about the completion of the inner state machine." +msgstr "" +"在上面的示例中， ``exit()`` 使状态机跳转到启动状态（内部隐藏状态）。这将通知 ``StateFsm`` 其" +"内部状态机已经完成。" #: ../../SpinalHDL/Libraries/fsm.rst:293 msgid "StateParallelFsm" @@ -271,12 +269,11 @@ msgstr "StateParallelFsm" #: ../../SpinalHDL/Libraries/fsm.rst:295 msgid "" -"``StateParallelFsm`` allows you to handle multiple nested state machines." -" When all nested state machine are done, statements in ``whenCompleted { " -"... }`` are executed." +"``StateParallelFsm`` allows you to handle multiple nested state machines. When all nested " +"state machine are done, statements in ``whenCompleted { ... }`` are executed." msgstr "" -"``StateParallelFsm`` 允许您处理多个嵌套状态机。当所有嵌套状态机完成时，执行 ``whenCompleted { ... " -"}`` 中的语句。" +"``StateParallelFsm`` 允许您处理多个嵌套状态机。当所有嵌套状态机完成时，执行 ``whenCompleted " +"{ ... }`` 中的语句。" #: ../../SpinalHDL/Libraries/fsm.rst:297 ../../SpinalHDL/Libraries/fsm.rst:322 msgid "Example:" @@ -288,32 +285,33 @@ msgstr "关于入口状态的注释" #: ../../SpinalHDL/Libraries/fsm.rst:310 msgid "" -"The way the entry state has been defined above makes it so that between " -"the reset and the first clock sampling, the state machine is in a boot " -"state. It is only after the first clock sampling that the defined entry " -"state becomes active. This allows to properly enter the entry state " -"(applying statements in ``onEntry``), and allows nested state machines." +"The way the entry state has been defined above makes it so that between the reset and the " +"first clock sampling, the state machine is in a boot state. It is only after the first " +"clock sampling that the defined entry state becomes active. This allows to properly enter " +"the entry state (applying statements in ``onEntry``), and allows nested state machines." msgstr "" -"上面定义入口状态的方式使得在复位和第一次时钟采样之间，状态机处于启动状态。只有在第一次时钟采样之后，定义的入口状态才会变为活动状态。这保证了能正确进入入口状态（在" -" ``onEntry`` 中应用语句），并支持嵌套状态机。" +"上面定义入口状态的方式使得在复位和第一次时钟采样之间，状态机处于启动状态。只有在第一次时钟采" +"样之后，定义的入口状态才会变为活动状态。这保证了能正确进入入口状态（在 ``onEntry`` 中应用语" +"句），并支持嵌套状态机。" #: ../../SpinalHDL/Libraries/fsm.rst:312 -#, fuzzy msgid "" -"While it is useful, it is also possible to bypass that feature and " -"directly having a state machine booting into a user state." -msgstr "虽然它很有用，但也可以绕过该功能并直接让状态机启动到用户状态。" +"While it is useful, it is also possible to bypass that feature and directly having a state " +"machine booting into a user state." +msgstr "虽然它很有用，但也可以绕过该功能，直接让状态机启动到用户状态。" #: ../../SpinalHDL/Libraries/fsm.rst:314 msgid "" -"To do so, use `makeInstantEntry()` instead of defining a ``new State``. " -"This function returns the boot state, active directly after reset." -msgstr "为此，请使用 `makeInstantEntry()` 而不是定义 ``new State`` 。该函数返回启动状态，复位后直接激活。" +"To do so, use `makeInstantEntry()` instead of defining a ``new State``. This function " +"returns the boot state, active directly after reset." +msgstr "" +"为此，请使用 `makeInstantEntry()` 而不是定义 ``new State`` 。该函数返回启动状态，复位后直接" +"激活。" #: ../../SpinalHDL/Libraries/fsm.rst:317 msgid "" -"The ``onEntry`` of that state will only be called when it transitions " -"from another state to this state and not during boot." +"The ``onEntry`` of that state will only be called when it transitions from another state to " +"this state and not during boot." msgstr "该状态的 ``onEntry`` 仅在从另一个状态转换到该状态时调用，而不是在启动期间。" #: ../../SpinalHDL/Libraries/fsm.rst:320 @@ -321,16 +319,16 @@ msgid "During simulation, the boot state is always named ``BOOT``." msgstr "在仿真过程中，启动状态始终命名为 ``BOOT`` 。" #: ../../SpinalHDL/Libraries/fsm.rst:352 -#, fuzzy msgid "Notes about using state value" -msgstr "关于入口状态的注释" +msgstr "使用状态值的注意事项" #: ../../SpinalHDL/Libraries/fsm.rst:354 msgid "" -"In cases that users want to retrieve the state value for purpose, where " -"state value could be accessed by `stateReg`. However, the `stateReg` is " -"not initialized during elaboration of state machine, so any access of " -"`stateReg` directly could cause error. Use the `postBuild` method as " -"below can solve this problem." +"In cases that users want to retrieve the state value for purpose, where state value could " +"be accessed by `stateReg`. However, the `stateReg` is not initialized during elaboration of " +"state machine, so any access of `stateReg` directly could cause error. Use the `postBuild` " +"method as below can solve this problem." msgstr "" - +"在某些情况下，用户想要检索状态机的状态值，可以通过 `stateReg` 访问。然而，状态机在展开过程中" +"实例化，此时 `stateReg` 尚未初始化，因此直接访问 `stateReg` 会导致错误。使用如下的 " +"`postBuild` 方法可以解决这个问题。" From fb5c48bddb720a09b8d4df688e31bfb8acb7c2ec Mon Sep 17 00:00:00 2001 From: Yindong Date: Mon, 23 Dec 2024 10:57:53 +0800 Subject: [PATCH 2/3] translate pipeline addup. --- .../Libraries/Pipeline/introduction.po | 403 ++++++------------ 1 file changed, 128 insertions(+), 275 deletions(-) diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/introduction.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/introduction.po index 28f6cb9353..b7bef00115 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/introduction.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/introduction.po @@ -5,53 +5,44 @@ # msgid "" msgstr "" -"Project-Id-Version: SpinalHDL\n" +"Project-Id-Version: SpinalHDL\n" "Report-Msgid-Bugs-To: \n" "POT-Creation-Date: 2024-10-31 09:38+0000\n" -"PO-Revision-Date: 2024-03-01 05:00+0000\n" +"PO-Revision-Date: 2024-12-23 10:57+0800\n" "Last-Translator: Readon \n" +"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Language-Team: Chinese (Simplified) \n" -"Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" +"Plural-Forms: nplurals=1; plural=0;\n" "Generated-By: Babel 2.16.0\n" +"X-Generator: Poedit 3.4.4\n" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:3 msgid "Introduction" msgstr "简介" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:5 -msgid "" -"spinal.lib.misc.pipeline provides a pipelining API. The main advantages " -"over manual pipelining are :" +msgid "spinal.lib.misc.pipeline provides a pipelining API. The main advantages over manual pipelining are :" msgstr "spinal.lib.misc.pipeline提供了一套流水线API。相对于手动流水线它的主要优点是：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:7 msgid "" -"You don't have to predefine all the signal elements needed for the entire" -" staged system upfront. You can create and consume stagable signals in a " -"more ad hoc fashion as your design requires - without needing to refactor" -" all the intervening stages to know about the signal" +"You don't have to predefine all the signal elements needed for the entire staged system upfront. You can create and consume stagable signals in a more ad hoc " +"fashion as your design requires - without needing to refactor all the intervening stages to know about the signal" msgstr "您不必预先准备好整个流水系统中所需的所有信号元素。您可以根据设计需要，以更特别的方式创建和使用可分级的信号，而无需重构所有中间阶段来处理信号" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:8 msgid "" -"Signals of the pipeline can utilize the powerful parametrization " -"capabilities of SpinalHDL and be subject to optimization/removal if a " -"specific design build does not require a particular parametrized feature," -" without any need to modify the staging system design or project code " -"base in a significant way." -msgstr "流水线的信号可以利用SpinalHDL的强大参数化能力，并且如果设计构建中不需要特定的参数化特征，则可以进行优化/移除，而不需要以显著的方式修改流水系统设计或项目代码库。" +"Signals of the pipeline can utilize the powerful parametrization capabilities of SpinalHDL and be subject to optimization/removal if a specific design build does " +"not require a particular parametrized feature, without any need to modify the staging system design or project code base in a significant way." +msgstr "" +"流水线的信号可以利用SpinalHDL的强大参数化能力，并且如果设计构建中不需要特定的参数化特征，则可以进行优化/移除，而不需要以显著的方式修改流水系统设计或项目代码库。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:9 -#, fuzzy -msgid "" -"Manual retiming is much easier, as you don't have to handle the registers" -" / arbitration manually" -msgstr "手动时序调整要容易得多，因为您不必手动处理寄存器/仲裁器" +msgid "Manual retiming is much easier, as you don't have to handle the registers / arbitration manually" +msgstr "手动时序调整要容易得多，因为您不需要手动处理寄存器/仲裁器" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:10 msgid "Manage the arbitration by itself" @@ -74,17 +65,13 @@ msgid "Builder : which will generate the hardware required for a whole pipeline" msgstr "Builder：生成整个管道所需的硬件" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:17 -msgid "" -"Payload : which are used to retrieve hardware signals on nodes along the " -"pipeline" +msgid "Payload : which are used to retrieve hardware signals on nodes along the pipeline" msgstr "Payload：用于获取流水线的节点上的硬件信号" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:19 msgid "" -"It is important to understand that Payload isn't a hardware data/signal " -"instance, but a key to retrieve a data/signal on nodes along the " -"pipeline, and that the pipeline builder will then automatically " -"interconnect/pipeline every occurrence of a given Payload between nodes." +"It is important to understand that Payload isn't a hardware data/signal instance, but a key to retrieve a data/signal on nodes along the pipeline, and that the " +"pipeline builder will then automatically interconnect/pipeline every occurrence of a given Payload between nodes." msgstr "重要的是，Payload不是硬件数据/信号实例，而是用于检索流水线在节点中数据/信号的关键，并且流水线构建器随后将在节点之间的每次给定Payload出现时自动互连/流水线。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:21 @@ -124,19 +111,15 @@ msgid "Payload" msgstr "Payload" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:150 -#, fuzzy msgid "" -"Payload objects are used to refer to data which can go through the " -"pipeline. Technically speaking, Payload is a HardType which has a name " -"and is used as a \"key\" to retrieve the signals in a certain pipeline " -"stage." +"Payload objects are used to refer to data which can go through the pipeline. Technically speaking, Payload is a HardType which has a name and is used as a " +"\"key\" to retrieve the signals in a certain pipeline stage." msgstr "Payload对象用于引用可以通过流水线的数据。从技术上讲，Payload是一个HardType，它有一个名字，并被用作在流水线某个级中检索信号的“键”。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:163 msgid "" -"Note that I got used to name the Payload instances using uppercase. This " -"is to make it very explicit that the thing isn't a hardware signal, but " -"are more like a \"key/type\" to access things." +"Note that I got used to name the Payload instances using uppercase. This is to make it very explicit that the thing isn't a hardware signal, but are more like a " +"\"key/type\" to access things." msgstr "请注意，我习惯于使用大写对Payload实例命名。这是为了让它非常明确，这不是一个硬件信号，更像是一个“键/类型”访问的东西。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:166 @@ -144,19 +127,15 @@ msgid "Node" msgstr "Node" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:168 -msgid "" -"Node mostly hosts the valid/ready arbitration signals, and the hardware " -"signals required for all the Payload values going through it." +msgid "Node mostly hosts the valid/ready arbitration signals, and the hardware signals required for all the Payload values going through it." msgstr "Node主要托管有效/就绪仲裁信号，以及所有通过它的硬件信号所需的Payload。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:170 msgid "You can access its arbitration via :" msgstr "您可以通过以下方式访问其仲裁器：" -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:177 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:238 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:268 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:390 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:177 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:238 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:268 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:390 #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:427 msgid "API" msgstr "API" @@ -165,12 +144,9 @@ msgstr "API" msgid "Access" msgstr "访问" -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:179 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:218 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:239 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:269 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:391 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:428 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:179 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:218 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:239 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:269 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:391 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:428 msgid "Description" msgstr "描述" @@ -178,18 +154,15 @@ msgstr "描述" msgid "node.valid" msgstr "node.valid" -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:181 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:184 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:181 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:184 #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:187 msgid "RW" msgstr "RW" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:182 msgid "" -"Is the signal which specifies if a transaction is present on the node. It" -" is driven by the upstream. Once asserted, it must only be de-asserted " -"the cycle after which either both valid and ready or node.cancel are " -"high. valid must not depend on ready." +"Is the signal which specifies if a transaction is present on the node. It is driven by the upstream. Once asserted, it must only be de-asserted the cycle after " +"which either both valid and ready or node.cancel are high. valid must not depend on ready." msgstr "指定节点上是否存在事务的信号。它是由上游逻辑驱动的。一旦置为1，则它必须且仅能在valid和ready同时置位或node.cancel为高的周期后解除置位。valid不依赖于ready。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:183 @@ -197,13 +170,10 @@ msgid "node.ready" msgstr "node.ready" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:185 -#, fuzzy msgid "" -"Is the signal which specifies if the node's transaction can proceed " -"downstream. It is driven by the downstream to create backpressure. The " -"signal has no meaning when there is no transaction (node.valid being " -"deasserted)" -msgstr "指定节点的事务是否可以向下游进行的信号。它是由下游驱动以创建反压。当没有事务（node.valid被置0）时，该信号无意义" +"Is the signal which specifies if the node's transaction can proceed downstream. It is driven by the downstream to create backpressure. The signal has no meaning " +"when there is no transaction (node.valid being deasserted)" +msgstr "表示节点中的事务是否可以向下游传递的信号。它由下游驱动以创建反压。当没有事务（node.valid被置0）时，该信号无意义" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:186 msgid "node.cancel" @@ -211,21 +181,17 @@ msgstr "node.cancel" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:188 msgid "" -"Is the signal which specifies if the node's transaction in being canceled" -" from the pipeline. It is driven by the downstream. The signal has no " -"meaning when there is no transaction (node.valid being deasserted)" +"Is the signal which specifies if the node's transaction in being canceled from the pipeline. It is driven by the downstream. The signal has no meaning when there " +"is no transaction (node.valid being deasserted)" msgstr "指定节点的事务是否正在从流水线中取消的信号。它由下游驱动。当没有事务时（node.valid被置0），该信号没有意义" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:189 msgid "node.isValid" msgstr "node.isValid" -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:190 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:193 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:196 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:199 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:202 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:207 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:190 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:193 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:196 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:199 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:202 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:207 msgid "RO" msgstr "RO" @@ -254,11 +220,8 @@ msgid "node.isFiring" msgstr "node.isFiring" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:200 -#, fuzzy -msgid "" -"True when the node transaction is successfully moving further (valid && " -"ready && !cancel). Useful to commit state changes." -msgstr "当节点事务成功继续进行时为True（valid && ready && !cancel）。用于提交状态更改。" +msgid "True when the node transaction is successfully moving further (valid && ready && !cancel). Useful to commit state changes." +msgstr "当节点事务成功继续传递时为True（valid && ready && !cancel）。提交状态更改时非常有用。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:201 msgid "node.isMoving" @@ -266,46 +229,35 @@ msgstr "node.isMoving" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:203 msgid "" -"True when the node transaction will not be present anymore on the node " -"(starting from the next cycle), either because downstream is ready to " -"take the transaction, or because the transaction is canceled from the " -"pipeline. (valid && (ready || cancel)). Useful to \"reset\" states." +"True when the node transaction will not be present anymore on the node (starting from the next cycle), either because downstream is ready to take the " +"transaction, or because the transaction is canceled from the pipeline. (valid && (ready || cancel)). Useful to \"reset\" states." msgstr "" -"当节点事务将不再存在于节点上时（从下一周期开始）为True，要么是因为下游准备好接收事务，要么是因为事务已从流水线中取消。（valid && " -"(ready || cancel)）用于“复位”(reset)状态。" +"当节点事务将不再存在于节点上时（从下一周期开始）为True，要么是因为下游准备好接收事务，要么是因为事务已从流水线中取消。（valid && (ready || cancel)）用于“复" +"位”(reset)状态。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:206 msgid "node.isCanceling" msgstr "node.isCanceling" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:208 -msgid "" -"True when the node transaction is being canceled. Meaning that it will " -"not appear anywhere in the pipeline in future cycles." +msgid "True when the node transaction is being canceled. Meaning that it will not appear anywhere in the pipeline in future cycles." msgstr "当节点事务正在被取消时为True。这意味着在将来的周期中它不会出现在流水线中的任何地方。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:210 -msgid "" -"Note that the node.valid/node.ready signals follows the same conventions " -"than the :doc:`../stream`'s ones ." +msgid "Note that the node.valid/node.ready signals follows the same conventions than the :doc:`../stream`'s ones ." msgstr "请注意，node.valid/node.ready信号遵循与 :doc:`../stream` 中相同的规范。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:212 -#, fuzzy msgid "" -"The Node controls (valid/ready/cancel) and status (isValid, isReady, " -"isCancel, isFiring, ...) signals are created on demand. So for instance " -"you can create pipeline with no backpressure by never referring to the " -"ready signal. That's why it is important to use status signals when you " -"want to read the status of something and only use control signals when " -"you to drive something." -msgstr "Node的控制信号（valid/ready/cancel）和状态信号（isValid、isReady、isCancel、isFiring等）是按需创建的。因此，例如，您可以通过永远不引用ready信号来创建没有反压的流水线。这就是在想要读取某物的状态时使用状态信号，仅在想要驱动某物时使用控制信号的重要性所在。" +"The Node controls (valid/ready/cancel) and status (isValid, isReady, isCancel, isFiring, ...) signals are created on demand. So for instance you can create " +"pipeline with no backpressure by never referring to the ready signal. That's why it is important to use status signals when you want to read the status of " +"something and only use control signals when you to drive something." +msgstr "" +"Node的控制信号（valid/ready/cancel）和状态信号（isValid、isReady、isCancel、isFiring等）是按需创建的。因此，当您想要读取某事物的状态时，使用状态信号很重要，只有当" +"您想要驱动某事物时才使用控制信号。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:215 -msgid "" -"Here is a list of arbitration cases you can have on a node. " -"valid/ready/cancel define the state we are in, while isFiring/isMoving " -"result of those :" +msgid "Here is a list of arbitration cases you can have on a node. valid/ready/cancel define the state we are in, while isFiring/isMoving result of those :" msgstr "以下是节点上可能出现的仲裁情况列表。valid/ready/cancel定义了我们所处的状态，而isFiring/isMoving是这些状态的结果：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:218 @@ -328,15 +280,12 @@ msgstr "isFiring" msgid "isMoving" msgstr "isMoving" -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:220 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:222 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:224 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:226 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:220 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:222 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:224 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:226 msgid "0" msgstr "0" -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:220 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:226 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:220 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:226 msgid "X" msgstr "X" @@ -344,8 +293,7 @@ msgstr "X" msgid "No transaction" msgstr "无事务" -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:222 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:224 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:222 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:224 #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:226 msgid "1" msgstr "1" @@ -364,9 +312,8 @@ msgstr "取消" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:230 msgid "" -"Note that if you want to model things like for instance a CPU stage which" -" can block and flush stuff, take a look a the CtrlLink, as it provides " -"the API to do such things." +"Note that if you want to model things like for instance a CPU stage which can block and flush stuff, take a look a the CtrlLink, as it provides the API to do " +"such things." msgstr "请注意，如果您想要建模诸如CPU级可能的阻塞和刷新的情况，可以查看 CtrlLink，因为它提供了执行此类操作的 API。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:232 @@ -387,10 +334,8 @@ msgstr "node(Payload, Any)" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:243 msgid "" -"Same as above, but include a second argument which is used as a " -"\"secondary key\". This eases the construction of multi-lane hardware. " -"For instance, when you have a multi issue CPU pipeline, you can use the " -"lane Int id as secondary key" +"Same as above, but include a second argument which is used as a \"secondary key\". This eases the construction of multi-lane hardware. For instance, when you " +"have a multi issue CPU pipeline, you can use the lane Int id as secondary key" msgstr "与上述相同，但包括一个用作“次要键”的第二个参数。这有助于构建多通道硬件。例如，当您有一个多发射CPU流水线时，您可以使用通道Int id作为次要键" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:244 @@ -398,18 +343,12 @@ msgid "node.insert(Data)" msgstr "node.insert(Data)" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:245 -msgid "" -"Return a new Payload instance which is connected to the given Data " -"hardware signal" +msgid "Return a new Payload instance which is connected to the given Data hardware signal" msgstr "返回一个新的Payload实例，该实例连接到给定的Data硬件信号" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:261 -#, fuzzy -msgid "" -"While you can manually drive/read the arbitration/data of the first/last " -"stage of your pipeline, there is a few utilities to connect its " -"boundaries." -msgstr "虽然您可以手动驱动/读取流水线的第一个/最后一级的仲裁/数据，但有一些实用工具可以连接其边界。" +msgid "While you can manually drive/read the arbitration/data of the first/last stage of your pipeline, there is a few utilities to connect its boundaries." +msgstr "您不仅可以手动方式来驱动/读取流水线的第一/最后一级的仲裁信号/数据，也有一些实用工具可以连接这些边界上的级。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:270 msgid "node.arbitrateFrom(Stream[T]])" @@ -448,17 +387,14 @@ msgid "node.driveFrom(Stream[T]])((Node, T) => Unit)" msgstr "node.driveFrom(Stream[T]])((Node, T) => Unit)" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:279 -msgid "" -"Drive a node from a stream. The provided lambda function can be use to " -"connect the data" +msgid "Drive a node from a stream. The provided lambda function can be use to connect the data" msgstr "由反压流驱动节点。提供的lambda函数可以用于连接数据" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:280 msgid "node.driveFrom(Flow[T]])((Node, T) => Unit)" msgstr "node.driveFrom(Flow[T]])((Node, T) => Unit)" -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:281 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:285 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:281 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:285 msgid "Same as above but for Flow" msgstr "与上述类似，但适用于Flow" @@ -467,9 +403,7 @@ msgid "node.driveTo(Stream[T]])((T, Node) => Unit)" msgstr "node.driveTo(Stream[T]])((T, Node) => Unit)" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:283 -msgid "" -"Drive a stream from the node. The provided lambda function can be use to " -"connect the data" +msgid "Drive a stream from the node. The provided lambda function can be use to connect the data" msgstr "由节点驱动反压流。提供的lambda函数可以用于连接数据" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:284 @@ -478,9 +412,8 @@ msgstr "node.driveTo(Flow[T]])((T, Node) => Unit)" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:305 msgid "" -"In order to reduce verbosity, there is a set of implicit conversions " -"between Payload toward their data representation which can be used when " -"you are in the context of a Node :" +"In order to reduce verbosity, there is a set of implicit conversions between Payload toward their data representation which can be used when you are in the " +"context of a Node :" msgstr "为了减少冗长，在Payload与其数据表示之间有一组隐式转换，可在Node下使用：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:314 @@ -488,17 +421,12 @@ msgid "You can also use those implicit conversions by importing them :" msgstr "您还可以通过导入它们来使用这些隐式转换：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:327 -#, fuzzy msgid "" -"There is also an API which allows you to create new Area which provide " -"the whole API of a given node instance (including implicit conversion) " -"without import :" -msgstr "还有一个API，它允许你创建新的Area，这个Area提供了给定节点实例的全部API（包括隐式转换），而无需导入：" +"There is also an API which allows you to create new Area which provide the whole API of a given node instance (including implicit conversion) without import :" +msgstr "还有一个API，它允许你创建新的Area，这个Area无需导入就可提供给定节点实例的全部API（包括隐式转换）：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:338 -msgid "" -"Such feature is very useful when you have parametrizable pipeline " -"locations for your hardware (see retiming example)." +msgid "Such feature is very useful when you have parametrizable pipeline locations for your hardware (see retiming example)." msgstr "当硬件具有可参数化的流水线位置时，这样的功能非常有用（请参阅重定时示例）。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:342 @@ -507,13 +435,9 @@ msgstr "Links" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:344 msgid "" -"There is few different Links already implemented (but you could also " -"create your own custom one). The idea of Links is to connect two nodes " -"together in various ways. They generally have a `up` Node and a `down` " -"Node." -msgstr "" -"目前已经实现了一些不同的Links（但您也可以创建自己的自定义Links）。Links的思想是以各种方式将两个节点连接在一起，它们通常有一个 " -"`up` 节点和一个 `down` 节点。" +"There is few different Links already implemented (but you could also create your own custom one). The idea of Links is to connect two nodes together in various " +"ways. They generally have a `up` Node and a `down` Node." +msgstr "目前已经实现了一些不同的Links（但您也可以创建自己的自定义Links）。Links的思想是以各种方式将两个节点连接在一起，它们通常有一个 `up` 节点和一个 `down` 节点。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:349 msgid "DirectLink" @@ -528,9 +452,7 @@ msgid "StageLink" msgstr "StageLink" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:363 -msgid "" -"This connect two nodes using registers on the data / valid signals and " -"some arbitration on the ready." +msgid "This connect two nodes using registers on the data / valid signals and some arbitration on the ready." msgstr "这使用data/valid信号上的寄存器和ready信号上的一些仲裁连接了两个节点。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:371 @@ -538,10 +460,7 @@ msgid "S2mLink" msgstr "S2mLink" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:373 -#, fuzzy -msgid "" -"This connect two nodes using registers on the ready signal, which can be " -"useful to improve backpressure combinatorial timings." +msgid "This connect two nodes using registers on the ready signal, which can be useful to improve backpressure combinatorial timings." msgstr "这使用ready信号上的寄存器连接两个节点，这对于改进反压组合时序非常有用。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:380 @@ -550,9 +469,8 @@ msgstr "CtrlLink" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:382 msgid "" -"This is kind of a special Link, as connect two nodes with optional flow " -"control / bypass logic. Its API should be flexible enough to implement a " -"CPU stage with it." +"This is kind of a special Link, as connect two nodes with optional flow control / bypass logic. Its API should be flexible enough to implement a CPU stage with " +"it." msgstr "这是一种特殊的 Link，用于连接两个节点，具有可选的流量控制/旁路逻辑。它的应用程序接口应该足够灵活，可以用它来实现 CPU 流水级。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:384 @@ -572,9 +490,7 @@ msgid "throwWhen(Bool)" msgstr "throwWhen(Bool)" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:395 -msgid "" -"Allows to cancel the current transaction from the pipeline (clear " -"down.valid and make the transaction driver forget its current state)" +msgid "Allows to cancel the current transaction from the pipeline (clear down.valid and make the transaction driver forget its current state)" msgstr "允许从流水线中取消当前事务（清除 down.valid，使事务驱动逻辑忘记其当前状态）" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:396 @@ -582,9 +498,7 @@ msgid "forgetOneWhen(Bool)" msgstr "forgetOneWhen(Bool)" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:397 -msgid "" -"Allows to request the upstream to forget its current transaction (but " -"doesn't clear the down.valid)" +msgid "Allows to request the upstream to forget its current transaction (but doesn't clear the down.valid)" msgstr "允许请求上游节点忘记其当前事务（但不会清除 down.valid）" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:398 @@ -612,23 +526,15 @@ msgid "Allows to hide the current transaction from downstream (clear down.valid) msgstr "允许下游节点隐藏当前传输事务（清零 down.valid）" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:405 -msgid "" -"Also note that if you want to do flow control in a conditional scope (ex " -"in a when statement), you can call the following functions :" +msgid "Also note that if you want to do flow control in a conditional scope (ex in a when statement), you can call the following functions :" msgstr "还要注意的是，如果要在条件作用域（例如在 when 语句中）进行通信流控制，可以调用以下函数 ：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:407 -msgid "" -"haltIt(), duplicateIt(), terminateIt(), forgetOneNow(), ignoreReadyNow()," -" throwIt()" -msgstr "" -"haltIt(), duplicateIt(), terminateIt(), forgetOneNow(), ignoreReadyNow()," -" throwIt()" +msgid "haltIt(), duplicateIt(), terminateIt(), forgetOneNow(), ignoreReadyNow(), throwIt()" +msgstr "haltIt(), duplicateIt(), terminateIt(), forgetOneNow(), ignoreReadyNow(), throwIt()" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:419 -msgid "" -"You can retrieve which nodes are connected to the Link using node.up / " -"node.down." +msgid "You can retrieve which nodes are connected to the Link using node.up / node.down." msgstr "您可以使用 node.up / node.down 查看哪些节点连接到了链接。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:421 @@ -664,17 +570,11 @@ msgid "link.bypass(Payload)" msgstr "link.bypass(Payload)" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:436 -#, fuzzy -msgid "" -"Allows to conditionally override a Payload value between link.up -> " -"link.down. This can be used to fix data hazard in CPU pipelines for " -"instance." +msgid "Allows to conditionally override a Payload value between link.up -> link.down. This can be used to fix data hazard in CPU pipelines for instance." msgstr "允许在 link.up -> link.down 之间有条件地覆盖 Payload 值。例如，这可用于修复 CPU 流水线中的数据冲突。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:455 -msgid "" -"Note that if you create a CtrlLink without node arguments, it will create" -" its own nodes internally." +msgid "Note that if you create a CtrlLink without node arguments, it will create its own nodes internally." msgstr "请注意，如果创建的 CtrlLink 不带节点参数，它将在内部创建自己的节点。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:466 @@ -698,76 +598,61 @@ msgid "But that API may change a bit, as it is still fresh." msgstr "不过，由于 API 还很新，后面可能会有一些变化。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:489 -#, fuzzy msgid "Builders" -msgstr "Builder" +msgstr "Builders" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:491 -msgid "" -"To generate the hardware of your pipeline, you need to give a list of all" -" the Links used in your pipeline." +msgid "To generate the hardware of your pipeline, you need to give a list of all the Links used in your pipeline." msgstr "要生成流水线硬件，您需要提供流水线中使用的所有链接列表。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:506 -#, fuzzy -msgid "" -"There is also a set of \"all in one\" builders that you can instantiate " -"to help yourself." +msgid "There is also a set of \"all in one\" builders that you can instantiate to help yourself." msgstr "此外，还有一套 \"一体化 \"的构建工具，您可以利用它来帮助你自己。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:509 -#, fuzzy msgid "StagePipeline" -msgstr "StageLink" +msgstr "StagePipeline" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:511 msgid "" -"For instance there is the StagePipeline class which serve two purposes : " -"- It ease the creation of simple pipelines which are composed of : Node " -"-> StageLink -> Node -> StageLink -> ... - It extends the pipeline length" -" on the fly" +"For instance there is the StagePipeline class which serve two purposes : - It ease the creation of simple pipelines which are composed of : Node -> StageLink -> " +"Node -> StageLink -> ... - It extends the pipeline length on the fly" msgstr "" +"例如，StagePipeline 类有两个作用： - 它便于创建简单的流水线，这些流水线由后面部分组成：Node -> StageLink -> Node -> StageLink -> ... - 它可以动态地扩展流水线长度" -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:515 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:555 -#, fuzzy +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:515 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:555 msgid "Here is an example which :" -msgstr "以下是一个用于阐述的例子：" +msgstr "以下是一个例子：" -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:517 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:557 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:517 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:557 msgid "Take the input at stage 0" -msgstr "" +msgstr "获取第 0 级输入" -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:518 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:558 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:518 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:558 msgid "Sum the input at stage 1" -msgstr "" +msgstr "对第 1 级输入求和" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:519 msgid "Square the sum at stage 2" -msgstr "" +msgstr "对第 2 级输入求平方和" -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:520 -#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:560 +#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:520 ../../SpinalHDL/Libraries/Pipeline/introduction.rst:560 msgid "Provide the result at stage 3" -msgstr "" +msgstr "在第 3 级提供结果" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:551 -#, fuzzy msgid "StageCtrlPipeline" -msgstr "StageLink" +msgstr "StageCtrlPipeline" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:553 msgid "" -"Very similar to StagePipeline, but it replace Nodes by StageLink, " -"allowing to handle the arbitration / bypasses on each stages, which is " -"for instance quite usefull for CPU designs." -msgstr "" +"Very similar to StagePipeline, but it replace Nodes by StageLink, allowing to handle the arbitration / bypasses on each stages, which is for instance quite " +"usefull for CPU designs." +msgstr "与 StagePipeline 非常相似，但它用 StageLink 代替了 Nodes，允许在每个阶段上处理仲裁/旁路，这在 CPU 设计中非常有用。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:559 msgid "Check the sum value and eventualy drop the transaction at stage 2" -msgstr "" +msgstr "检查总和值，最终在第2级放弃该次传输" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:593 msgid "Composability" @@ -775,47 +660,34 @@ msgstr "组合能力（Composability）" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:595 msgid "" -"One good thing about the API is that it easily allows to compose a " -"pipeline with multiple parallel things. What i mean by \"compose\" is " -"that sometime the pipeline you need to design has parallel processing to " -"do." +"One good thing about the API is that it easily allows to compose a pipeline with multiple parallel things. What i mean by \"compose\" is that sometime the " +"pipeline you need to design has parallel processing to do." msgstr "该API的一个优点是，它可以轻松地将多个并行事物组成一个流水线。这里的 \"组成 \"是指有时你设计的流水线需要进行并行处理。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:597 msgid "" -"Imagine you need to do floating point multiplication on 4 pairs of " -"numbers (to later sum them). If those 4 pairs a provided at the same time" -" by a single stream of data, then you don't want 4 different pipelines to" -" multiply them, instead you want to process them all in parallel in the " -"same pipeline." +"Imagine you need to do floating point multiplication on 4 pairs of numbers (to later sum them). If those 4 pairs a provided at the same time by a single stream " +"of data, then you don't want 4 different pipelines to multiply them, instead you want to process them all in parallel in the same pipeline." msgstr "" -"试想一下，如果您需要对 4 对数字进行浮点乘法运算（稍后求和）。并且这 4 对数字是由一个数据流同时提供的，那么就不需要 4 " -"条不同的流水线来进行乘法运算，而需要在同一条流水线上并行处理。" +"试想一下，如果您需要对 4 对数字进行浮点乘法运算（稍后求和）。并且这 4 对数字是由一个数据流同时提供的，那么就不需要 4 条不同的流水线来进行乘法运算，而需要在同一条" +"流水线上并行处理。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:599 -msgid "" -"The example below show a pattern which composes a pipeline with multiple " -"lanes to process them in parallel." +msgid "The example below show a pattern which composes a pipeline with multiple lanes to process them in parallel." msgstr "下面的示例展示了一种模式，它将多个通道组成一个流水线，来并行处理它们。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:643 -#, fuzzy -msgid "" -"This will produce the following data path (assuming lanesCount = 2), " -"arbitration not being shown :" -msgstr "这将产生以下数据路径（假设 lanesCount = 2），仲裁器没有显示：" +msgid "This will produce the following data path (assuming lanesCount = 2), arbitration not being shown :" +msgstr "这将产生以下数据路径（假设 lanesCount = 2），这里没有给出仲裁：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:650 -#, fuzzy msgid "Retiming / Variable length" msgstr "重定时/可变长度" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:652 msgid "" -"Sometime you want to design a pipeline, but you don't really know where " -"the critical paths will be and what the right balance between stages is. " -"And often you can't rely on the synthesis tool doing a good job with " -"automatic retiming." +"Sometime you want to design a pipeline, but you don't really know where the critical paths will be and what the right balance between stages is. And often you " +"can't rely on the synthesis tool doing a good job with automatic retiming." msgstr "有时，你想设计一个流水线，但你并不真正知道关键路径在哪里，也不知道各阶段之间如何平衡。而且通常情况下，你无法依赖综合工具做好自动重定时工作。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:654 @@ -831,23 +703,17 @@ msgid "If then you generate this component like this :" msgstr "如果像这样生成该组件：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:731 -msgid "" -"You will get a 4 stages separated by 3 layer of flip flop doing your " -"processing :" +msgid "You will get a 4 stages separated by 3 layer of flip flop doing your processing :" msgstr "您将获得由 3 层寄存器（flip flop）分隔的 4 个处理阶段：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:736 -msgid "" -"Note the generated hardware verilog is kinda clean (by my standards at " -"least :P) :" +msgid "Note the generated hardware verilog is kinda clean (by my standards at least :P) :" msgstr "请注意，生成的硬件 verilog 还算干净（至少按我的标准来说是这样 :P）：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:851 msgid "" -"Also, you can easily tweak how many stages and where you want the " -"processing to be done, for instance you may want to move the inversion " -"hardware in the same stage as the adder. This can be done the following " -"way :" +"Also, you can easily tweak how many stages and where you want the processing to be done, for instance you may want to move the inversion hardware in the same " +"stage as the adder. This can be done the following way :" msgstr "此外，您还可以轻松调整处理的级数和位置，例如，您可能希望将翻转的硬件逻辑移到与加法器相同级上。具体方法如下：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:865 @@ -855,19 +721,12 @@ msgid "Then you may want to remove the output register stage :" msgstr "那么您可能需要移除输出寄存器级：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:879 -msgid "" -"One thing about this example is the necessity intermediate val as " -"`addNode`. I mean :" +msgid "One thing about this example is the necessity intermediate val as `addNode`. I mean :" msgstr "这个示例的一个特点是，中间值必须是 `addNode`。例如：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:889 -#, fuzzy -msgid "" -"Unfortunately, scala doesn't allow to replace `new addNode.Area` with " -"`new nodes(addAt).Area`. One workaround is to define a class as :" -msgstr "" -"遗憾的是，scala 不允许用 `new nodes(addAt).Area` 替换 `new " -"addNode.Area`。一种变通方法是将其定义为一个类，比如：" +msgid "Unfortunately, scala doesn't allow to replace `new addNode.Area` with `new nodes(addAt).Area`. One workaround is to define a class as :" +msgstr "遗憾的是，scala 不允许用 `new nodes(addAt).Area` 替换 `new addNode.Area`。一种变通方法是将其定义为一个类，比如：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:899 msgid "Depending the scale of your pipeline, it can payoff." @@ -894,14 +753,8 @@ msgid "add / jump / led /delay instructions" msgstr "add / jump / led /delay 指令" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:979 -msgid "" -"Here is a simple testbench which implement a loop which will make the led" -" counting up." +msgid "Here is a simple testbench which implement a loop which will make the led counting up." msgstr "下面是一个简单的测试平台，它实现了一个循环，使 led 计数值上升。" -#~ msgid "" -#~ "For instance there is the NodesBuilder" -#~ " class which can be used to " -#~ "create sequentially staged pipelines :" +#~ msgid "For instance there is the NodesBuilder class which can be used to create sequentially staged pipelines :" #~ msgstr "例如，有一个 NodesBuilder 类，可用于创建按顺序分级的流水线：" - From 1c16da1b5442320bd61b61c4c77f04a56fafd6b8 Mon Sep 17 00:00:00 2001 From: Yindong Date: Mon, 23 Dec 2024 11:00:04 +0800 Subject: [PATCH 3/3] translate assert description. --- .../Other language features/assertion.po | 28 +++++++++++-------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/assertion.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/assertion.po index 372d87e99e..455c4f32da 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/assertion.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/assertion.po @@ -1,4 +1,3 @@ - msgid "" msgstr "" "Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" @@ -8,28 +7,30 @@ msgstr "" "Type:text/plain; charset=UTF-8\n" "Report-Msgid-Bugs-To: EMAIL@ADDRESS\n" "POT-Creation-Date: 2024-12-10 14:23+0000\n" -"PO-Revision-Date: 2023-12-18 07:38+0000\n" +"PO-Revision-Date: 2024-12-23 10:59+0800\n" "Last-Translator: Readon \n" +"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Language-Team: Chinese (Simplified) \n" -"Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" +"Plural-Forms: nplurals=1; plural=0;\n" "Generated-By: Babel 2.16.0\n" +"X-Generator: Poedit 3.4.4\n" #: ../../SpinalHDL/Other features/assertion.rst:3 language msgid "Assertions" msgstr "Assertions" #: ../../SpinalHDL/Other features/assertion.rst:5 language -#, fuzzy msgid "" "In addition to Scala run-time assertions `assert(condition : Boolean, " "message : String)`, you can add hardware assertions using the following " "syntax:" -msgstr "除了 Scala 运行时断言之外，您还可以使用以下语法添加硬件断言：" +msgstr "" +"除了 Scala 运行时断言 `assert(condition : Boolean, message : String)`，还" +"可以使用以下语法添加硬件断言：" #: ../../SpinalHDL/Other features/assertion.rst:7 language msgid "" @@ -87,12 +88,15 @@ msgstr "用于报告致命情况并关闭仿真" msgid "" "One practical example could be to check that the ``valid`` signal of a " "handshake protocol never drops when ``ready`` is low:" -msgstr "一个实际的例子是检查当 ``ready`` 为低电平时，握手协议的 ``valid`` 信号不应该由高变低：" +msgstr "" +"一个实际的例子是检查当 ``ready`` 为低电平时，握手协议的 ``valid`` 信号不" +"应该由高变低：" #: ../../SpinalHDL/Other features/assertion.rst:48 language msgid "" -"Scala run time assertions `assert(condition : Boolean, message : String)`" -" do not provide support for a severity level, and if triggered, will " -"always stop the current elaboration/simulation." +"Scala run time assertions `assert(condition : Boolean, message : " +"String)` do not provide support for a severity level, and if triggered, " +"will always stop the current elaboration/simulation." msgstr "" - +"Scala 运行时断言 `assert(condition : Boolean, message : String)` 不支持严" +"重性级别，一旦触发，将始终停止当前例化/仿真。"