Digital Logic & System Design

This repository contains solutions to programming & hardware assignments given in IIT Delhi's digital logic & system design course.

Features

Assignment 1

• Building a stopwatch in VHDL

Assignment 2

• Designing a 3-layer multi-layer perceptron to recognize digits from the MNIST dataset.

Assignment 3

• Finding the legal region of minterms using a Karnaugh maps.

Assignment 4

• Find the largest common area for a set of minterms.

Assignment 5

• Solving a Karnaugh map using heuristics.

Lessons Learnt

• VHDL
• Principles of hardware design
• Python

Running Instructions

Running instructions are provided in the pdf files in each assignment's directory.

Contributors

• Nischay Diwan
• Srijan Gupta