forked from dillonhuff/clockwork
-
Notifications
You must be signed in to change notification settings - Fork 0
/
conv33_naive_compute.v
223 lines (217 loc) · 7.21 KB
/
conv33_naive_compute.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
// Module `Mem` defined externally
module cu_input (
input clk,
input [15:0] in_inst_input_read [0:0],
output [15:0] buf_inst_input_write [0:0]
);
assign buf_inst_input_write[0] = in_inst_input_read[0];
endmodule
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg=init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= in;
end
assign out = outReg;
endmodule
module mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #(
parameter init = 16'h0000
) (
input [15:0] in,
input clk,
output [15:0] out
);
wire reg0_clk;
wire [15:0] reg0_in;
assign reg0_clk = clk;
assign reg0_in = in;
coreir_reg #(
.clk_posedge(1'b1),
.init(init),
.width(16)
) reg0 (
.clk(reg0_clk),
.in(reg0_in),
.out(out)
);
endmodule
module cu_output (
input clk,
input [15:0] buf_inst_output_read [8:0],
output [15:0] out_inst_output_write [0:0]
);
assign out_inst_output_write[0] = 16'((16'((16'((16'((16'((16'((16'((16'(buf_inst_output_read[0] + buf_inst_output_read[1])) + buf_inst_output_read[2])) + buf_inst_output_read[3])) + buf_inst_output_read[4])) + buf_inst_output_read[5])) + buf_inst_output_read[6])) + buf_inst_output_read[7])) + buf_inst_output_read[8]);
endmodule
module buf_inst_ub (
input clk,
input reset,
input [15:0] input_write [0:0],
output [15:0] output_read [8:0]
);
wire [15:0] d_reg__U10_in;
wire d_reg__U10_clk;
wire [15:0] d_reg__U10_out;
wire [15:0] d_reg__U11_in;
wire d_reg__U11_clk;
wire [15:0] d_reg__U11_out;
wire [15:0] d_reg__U12_in;
wire d_reg__U12_clk;
wire [15:0] d_reg__U12_out;
wire [15:0] d_reg__U13_in;
wire d_reg__U13_clk;
wire [15:0] d_reg__U13_out;
wire [15:0] d_reg__U8_in;
wire d_reg__U8_clk;
wire [15:0] d_reg__U8_out;
wire [15:0] d_reg__U9_in;
wire d_reg__U9_clk;
wire [15:0] d_reg__U9_out;
wire ub_buf_inst_input_10_to_buf_inst_output_3_rst_n;
wire ub_buf_inst_input_10_to_buf_inst_output_3_clk_en;
wire ub_buf_inst_input_10_to_buf_inst_output_3_clk;
wire [15:0] ub_buf_inst_input_10_to_buf_inst_output_3_data_in_0;
wire [15:0] ub_buf_inst_input_10_to_buf_inst_output_3_data_out_0;
wire [15:0] ub_buf_inst_input_10_to_buf_inst_output_3_data_out_1;
wire ub_buf_inst_input_10_to_buf_inst_output_3_flush;
assign d_reg__U10_in = ub_buf_inst_input_10_to_buf_inst_output_3_data_out_1;
assign d_reg__U10_clk = clk;
mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #(
.init(16'h0000)
) d_reg__U10 (
.in(d_reg__U10_in),
.clk(d_reg__U10_clk),
.out(d_reg__U10_out)
);
assign d_reg__U11_in = d_reg__U10_out;
assign d_reg__U11_clk = clk;
mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #(
.init(16'h0000)
) d_reg__U11 (
.in(d_reg__U11_in),
.clk(d_reg__U11_clk),
.out(d_reg__U11_out)
);
assign d_reg__U12_in = ub_buf_inst_input_10_to_buf_inst_output_3_data_out_0;
assign d_reg__U12_clk = clk;
mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #(
.init(16'h0000)
) d_reg__U12 (
.in(d_reg__U12_in),
.clk(d_reg__U12_clk),
.out(d_reg__U12_out)
);
assign d_reg__U13_in = d_reg__U12_out;
assign d_reg__U13_clk = clk;
mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #(
.init(16'h0000)
) d_reg__U13 (
.in(d_reg__U13_in),
.clk(d_reg__U13_clk),
.out(d_reg__U13_out)
);
assign d_reg__U8_in = input_write[0];
assign d_reg__U8_clk = clk;
mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #(
.init(16'h0000)
) d_reg__U8 (
.in(d_reg__U8_in),
.clk(d_reg__U8_clk),
.out(d_reg__U8_out)
);
assign d_reg__U9_in = d_reg__U8_out;
assign d_reg__U9_clk = clk;
mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #(
.init(16'h0000)
) d_reg__U9 (
.in(d_reg__U9_in),
.clk(d_reg__U9_clk),
.out(d_reg__U9_out)
);
assign ub_buf_inst_input_10_to_buf_inst_output_3_rst_n = 1'b0;
assign ub_buf_inst_input_10_to_buf_inst_output_3_clk_en = 1'b1;
assign ub_buf_inst_input_10_to_buf_inst_output_3_clk = clk;
assign ub_buf_inst_input_10_to_buf_inst_output_3_data_in_0 = input_write[0];
assign ub_buf_inst_input_10_to_buf_inst_output_3_flush = reset;
cwlib_Mem__confignull__has_flushTrue__has_resetFalse__has_stencil_validFalse__has_validFalse__num_input1__num_output2__width16 #(
.mode("lake")
) ub_buf_inst_input_10_to_buf_inst_output_3 (
.rst_n(ub_buf_inst_input_10_to_buf_inst_output_3_rst_n),
.clk_en(ub_buf_inst_input_10_to_buf_inst_output_3_clk_en),
.clk(ub_buf_inst_input_10_to_buf_inst_output_3_clk),
.data_in_0(ub_buf_inst_input_10_to_buf_inst_output_3_data_in_0),
.data_out_0(ub_buf_inst_input_10_to_buf_inst_output_3_data_out_0),
.data_out_1(ub_buf_inst_input_10_to_buf_inst_output_3_data_out_1),
.flush(ub_buf_inst_input_10_to_buf_inst_output_3_flush)
);
assign output_read[8] = input_write[0];
assign output_read[7] = d_reg__U8_out;
assign output_read[6] = d_reg__U9_out;
assign output_read[5] = ub_buf_inst_input_10_to_buf_inst_output_3_data_out_1;
assign output_read[4] = d_reg__U10_out;
assign output_read[3] = d_reg__U11_out;
assign output_read[2] = ub_buf_inst_input_10_to_buf_inst_output_3_data_out_0;
assign output_read[1] = d_reg__U12_out;
assign output_read[0] = d_reg__U13_out;
endmodule
module conv33_naive_compute (
input clk,
input reset,
output in_inst_input_read_en,
input [15:0] in_inst_input_read [0:0],
output out_inst_output_write_valid,
output [15:0] out_inst_output_write [0:0]
);
wire buf_inst_clk;
wire buf_inst_reset;
wire [15:0] buf_inst_input_write [0:0];
wire [15:0] buf_inst_output_read [8:0];
wire input_clk;
wire [15:0] input_in_inst_input_read [0:0];
wire [15:0] input_buf_inst_input_write [0:0];
wire output_clk;
wire [15:0] output_buf_inst_output_read [8:0];
wire [15:0] output_out_inst_output_write [0:0];
assign buf_inst_clk = clk;
assign buf_inst_reset = reset;
assign buf_inst_input_write[0] = input_buf_inst_input_write[0];
buf_inst_ub buf_inst (
.clk(buf_inst_clk),
.reset(buf_inst_reset),
.input_write(buf_inst_input_write),
.output_read(buf_inst_output_read)
);
assign input_clk = clk;
assign input_in_inst_input_read[0] = in_inst_input_read[0];
cu_input input (
.clk(input_clk),
.in_inst_input_read(input_in_inst_input_read),
.buf_inst_input_write(input_buf_inst_input_write)
);
assign output_clk = clk;
assign output_buf_inst_output_read[8] = buf_inst_output_read[8];
assign output_buf_inst_output_read[7] = buf_inst_output_read[7];
assign output_buf_inst_output_read[6] = buf_inst_output_read[6];
assign output_buf_inst_output_read[5] = buf_inst_output_read[5];
assign output_buf_inst_output_read[4] = buf_inst_output_read[4];
assign output_buf_inst_output_read[3] = buf_inst_output_read[3];
assign output_buf_inst_output_read[2] = buf_inst_output_read[2];
assign output_buf_inst_output_read[1] = buf_inst_output_read[1];
assign output_buf_inst_output_read[0] = buf_inst_output_read[0];
cu_output output (
.clk(output_clk),
.buf_inst_output_read(output_buf_inst_output_read),
.out_inst_output_write(output_out_inst_output_write)
);
assign in_inst_input_read_en = 1'b0;
assign out_inst_output_write_valid = 1'b0;
assign out_inst_output_write[0] = output_out_inst_output_write[0];
endmodule