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Merge branch 'master' into MICRO24_AHA_WS_LAKE
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@kalhankoul96
kalhankoul96 committed Oct 29, 2024
2 parents 82e66bb + f91c93f commit 81a9d46
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Showing 3 changed files with 8 additions and 102 deletions.
98 changes: 6 additions & 92 deletions lake/top/core_combiner.py
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Original file line number Diff line number Diff line change
Expand Up @@ -348,59 +348,11 @@ def get_config_mapping(self):
pipeline_scanner = False
fifo_depth = 8

# if pipeline_scanner:
# scan = ScannerPipe(data_width=data_width,
# fifo_depth=fifo_depth,
# add_clk_enable=True,
# defer_fifos=True,
# add_flush=False)
# else:
# scan = Scanner(data_width=data_width,
# fifo_depth=fifo_depth,
# defer_fifos=True,
# add_flush=False)

# wscan = WriteScanner(data_width=data_width,
# fifo_depth=fifo_depth,
# defer_fifos=True,
# add_flush=False)
# strg_ub = StrgUBThin(
# config_mode_str="pond",
# data_width=data_width, # CGRA Params
# mem_width=mem_width,
# mem_depth=mem_depth,
# input_addr_iterator_support=6,
# input_sched_iterator_support=6,
# output_addr_iterator_support=6,
# output_sched_iterator_support=6,
# interconnect_input_ports=1, # Connection to int
# interconnect_output_ports=1,
# config_width=16,
# read_delay=read_delay, # Cycle delay in read (SRAM vs Register File)
# rw_same_cycle=rw_same_cycle,
# gen_addr=True,
# comply_with_17=True,
# area_opt=False,
# area_opt_share=False,
# area_opt_dual_config=False,
# chaining=True,
# reduced_id_config_width=16,
# delay_width=4,
# iterator_support2=2 # assumes that this port has smaller iter_support
# )

strg_ub = StrgUBVec(data_width=16,
mem_width=64,
mem_depth=512)
# fiber_access = FiberAccess(data_width=16,
# local_memory=False,
# tech_map=GF_Tech_Map(depth=mem_depth, width=mem_width),
# defer_fifos=True)
# buffet = BuffetLike(data_width=16, mem_depth=mem_depth, local_memory=False,
# tech_map=GF_Tech_Map(depth=mem_depth, width=mem_width),
# mem_width=mem_width,
# defer_fifos=True,
# optimize_wide=True,
# add_flush=False)

strg_ram = StrgRAM(data_width=16,
banks=1,
memory_width=mem_width,
Expand All @@ -413,46 +365,8 @@ def get_config_mapping(self):

stencil_valid = StencilValid()

# controllers.append(scan)
# controllers.append(wscan)
# # controllers.append(buffet)

controllers.append(strg_ub)
# # controllers.append(fiber_access)
# controllers.append(strg_ram)
# controllers.append(stencil_valid)

# isect = Intersect(data_width=16,
# use_merger=False,
# fifo_depth=8,
# defer_fifos=True)
# crd_drop = CrdDrop(data_width=16, fifo_depth=8,
# lift_config=True,
# defer_fifos=True)
# crd_hold = CrdHold(data_width=16, fifo_depth=8,
# lift_config=True,
# defer_fifos=True,
# add_flush=False)
# onyxpe = OnyxPE(data_width=16, fifo_depth=8, defer_fifos=True, ext_pe_prefix="pe_prefix")
# repeat = Repeat(data_width=16,
# fifo_depth=8,
# defer_fifos=True)
# rsg = RepeatSignalGenerator(data_width=16,
# passthru=False,
# fifo_depth=8,
# defer_fifos=True)
# regcr = Reg(data_width=16,
# fifo_depth=8,
# defer_fifos=True)

# controllers_2 = []

# controllers_2.append(isect)
# controllers_2.append(crd_drop)
# controllers_2.append(crd_hold)
# controllers_2.append(onyxpe)
# controllers_2.append(repeat)
# controllers_2.append(rsg)
# controllers_2.append(regcr)

core_comb = CoreCombiner(data_width=16,
mem_width=mem_width,
Expand All @@ -470,10 +384,10 @@ def get_config_mapping(self):
fifo_depth=16,
tech_map_name=tech)

print(core_comb)
# print(core_comb)
core_comb_mapping = core_comb.dut.get_port_remap()
print(core_comb_mapping)
print(core_comb.get_modes_supported())
# print(core_comb_mapping)
# print(core_comb.get_modes_supported())

# config = extract_top_config(core_comb.dut, verbose=True)

Expand Down
2 changes: 0 additions & 2 deletions lake/top/fiber_access.py
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Original file line number Diff line number Diff line change
Expand Up @@ -483,8 +483,6 @@ def get_config_mode_str(self):

def get_bitstream(self, config_kwargs):

print("IN FLAVOR TOWN!!!")

assert 'flavor' in config_kwargs
flavor = config_kwargs['flavor']
vr_mode = config_kwargs['vr_mode']
Expand Down
10 changes: 2 additions & 8 deletions lake/top/memtile_builder.py
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Original file line number Diff line number Diff line change
Expand Up @@ -159,13 +159,10 @@ def finalize_controllers(self):
bulk_ctrl = 0
exclusive_ctrl = 0
for ctrl in self.controllers:
print(ctrl)
if ctrl.get_exclusive():
print("FOUND EXCLUSIVE")
self.ctrl_to_mode[ctrl.name] = (exclusive_ctrl, "excl")
exclusive_ctrl += 1
else:
print("FOUND BULK")
self.ctrl_to_mode[ctrl.name] = (bulk_ctrl, "bulk")
bulk_ctrl += 1
# self.num_modes = len(self.controllers)
Expand Down Expand Up @@ -302,8 +299,6 @@ def resolve_inputs(self):
stop_ded = self.size_to_port(ded)
self.add_io_dict(to_add=stop_ded, merged_dict=self.inputs_dict, mem_ctrl=mem_ctrl)

print("INPUTS DICT")
print(self.inputs_dict)

def resolve_outputs(self):
'''
Expand Down Expand Up @@ -911,7 +906,7 @@ def realize_inputs(self):
self.wire(new_input, self.controllers_flat_dict[ctrl_name].ports[port])

if any_rvs:
print(output_ready_map)
# print(output_ready_map)
self.create_mode_based_mux(out_sig=new_input_ready,
items=output_ready_map,
default=1)
Expand Down Expand Up @@ -1102,7 +1097,7 @@ def realize_outputs(self):
# Create the final output muxes
self.create_mode_based_mux(out_sig=new_output, items=output_data_map, default=0)
if any_rvs:
print(output_valid_map)
# print(output_valid_map)
self.create_mode_based_mux(out_sig=new_output_valid, items=output_valid_map, default=0)

# We need to choose which output is hooked up based on the mode...
Expand Down Expand Up @@ -1261,7 +1256,6 @@ def get_bitstream(self, config_json):
for idx, ctrl in enumerate(self.controllers):
if mode_used == ctrl.get_config_mode_str():
if not stencil_valid_used:
print(f"Found ctrl: {mode_used}")
config.append(("mode", idx))
break

Expand Down

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