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Add testbench files
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@mcoduoza
mcoduoza committed Nov 16, 2024
1 parent 531efb0 commit 832f281
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199 changes: 199 additions & 0 deletions tests/Makefile
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#!/bin/bash

# -------------------------------------------------------------------
# Variables
# -------------------------------------------------------------------
mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
mkfile_dir := $(dir $(mkfile_path))
lake_dir := $(mkfile_dir)/../lake

#module_dir := $(mkfile_dir)/../lake/modules
# garnet_dir := $(mkfile_dir)/../..
# gemstone_dir := $(realpath $(garnet_dir))/../gemstone
# netlist_dir := $(mkfile_dir)/netlist
# glc_dir := $(garnet_dir)/global_controller
# APP_ARGS ?= +APP0=app0

TOOL ?= VCS
TEST_TAR ?= 0
TOP ?= 0
TEST_UNIT ?= 0
INST ?= 0
NUM_INPUTS ?= 0
FIBER_ACCESS_ROOT ?= 0

export WAVEFORM ?= 1
# export WAVEFORM_GLB_ONLY ?= 0
# export SAIF ?= 0

# -------------------------------------------------------------------
# Compile Parameters
# -------------------------------------------------------------------
CLK_PERIOD ?= 1ns
TX_NUM_GLB ?= 1
TX_NUM_0 ?= 0
TX_NUM_1 ?= 0
TX_NUM_2 ?= 0
TX_NUM_3 ?= 0
SEG_MODE ?= 0

DESIGN_FILES += $(TEST_TAR) \
$(lake_dir)/modules/mu2f_iocore.sv

# DESIGN_FILES += $(module_dir)/$(TEST_UNIT)
#DESIGN_FILES += $(foreach unit,$(TEST_UNIT),$(module_dir)/$(unit))

# TB_FILES += -F tb/tb_cgra.f

# IP_FILES += -y /cad/cadence/GENUS_19.10.000_lnx86/share/synth/lib/chipware/sim/verilog/CW/ \
# -y /cad/cadence/GENUS_19.10.000_lnx86/share/synth/lib/chipware/sim/verilog/CWTECH/ \
# +libext+.v+.sv

# -------------------------------------------------------------------
# GLS Parameters
# -------------------------------------------------------------------
# GLB_TOP ?= glb_top
# GLB_TILE ?= glb_tile
# TILE_ARRAY ?= tile_array
# TILE_PE ?= Tile_PE
# TILE_MEM ?= Tile_MemCore
# NETLIST_FILES ?= -v $(garnet_dir)/garnet.v -v $(netlist_dir)/glb_top.vcs.v -v $(netlist_dir)/glb_tile.vcs.v \
# -v $(netlist_dir)/global_controller.vcs.v -v $(netlist_dir)/tile_array.vcs.v -v $(netlist_dir)/Tile_PE.vcs.v -v $(netlist_dir)/Tile_MemCore.vcs.v \
# -v $(netlist_dir)/sram.v -v $(netlist_dir)/tile_array.sram.v -v $(netlist_dir)/stdcells.v -v $(netlist_dir)/stdcells-lvt.v -v $(netlist_dir)/stdcells-ulvt.v -v $(netlist_dir)/stdcells-pm.v

# -------------------------------------------------------------------
# Run Parameters
# -------------------------------------------------------------------
# RUN_ARGS ?=
# RUN_LOG ?= run.log

# -------------------------------------------------------------------
# Command
# -------------------------------------------------------------------


WAVEFORM_ARGS = -debug_access+all -kdb +vpi +memcbk +vcsd


# Picked XRUN by a "coin"
VCS = vcs \
-sverilog \
$(TIMESCALE) \
-full64 \
-ldflags "-Wl,--no-as-needed" \
-CFLAGS "-m64" \
-top $(TOP) \
+vcs+lic+wait \
+vcs+initreg+random \
+overlap \
+v2k \
-l vcs.log \
$(WAVEFORM_ARGS) \
$(COMPILE_ARGS) \
$(INPUT_ARGS)

XRUN = xrun \
-64bit \
-sv \
-timescale 1ns/1ps \
-debug \
-sysv \
-top $(TOP) \
-elaborate \
-l xrun.log \
-covoverwrite \
+maxdelays \
-notimingchecks \
$(COMPILE_ARGS) \
$(INPUT_ARGS)

# -------------------------------------------------------------------
# C API
# -------------------------------------------------------------------
# .PHONY: libcgra.so
# libcgra.so: $(shell find lib -type f) $(garnet_dir)/global_buffer/header/global_buffer_param.h $(garnet_dir)/global_buffer/header/glb.h $(garnet_dir)/global_controller/header/glc.h
# gcc -Wno-error -Wall lib/*.c -I$(garnet_dir)/global_buffer/header -I$(garnet_dir)/global_controller/header -shared -o libcgra.so -fPIC

# -------------------------------------------------------------------
# Compile & Run
# -------------------------------------------------------------------
COMPILE_RTL_ARGS += +define+CLK_PERIOD=$(CLK_PERIOD) \
+define+TX_NUM_GLB=$(TX_NUM_GLB) \
+define+FIBER_ACCESS_ROOT=$(FIBER_ACCESS_ROOT) \
+define+TX_NUM_0=$(TX_NUM_0) \
+define+TX_NUM_1=$(TX_NUM_1) \
+define+TX_NUM_2=$(TX_NUM_2) \
+define+TX_NUM_3=$(TX_NUM_3) \
+define+SEG_MODE=$(SEG_MODE)

COMPILE_GLS_ARGS += +define+CLK_PERIOD=$(CLK_PERIOD) \
+define+TX_NUM_GLB=$(TX_NUM_GLB) \
+define+TX_NUM_0=$(TX_NUM_0) \
+define+TX_NUM_1=$(TX_NUM_1) \
+define+TX_NUM_2=$(TX_NUM_2) \
+define+TX_NUM_3=$(TX_NUM_3) \
+define+SEG_MODE=$(SEG_MODE)

ifeq ($(TOOL), XCELIUM)
COMPILE = $(XRUN)
# COMPILE_RTL_ARGS += -xminitialize 0 -xminit_log init.log -nospecify
# COMPILE_GLS_ARGS += -xminitialize 0 -xminit_log init.log
# COMPILE_GLS_ARGS += -ALLOWREDEFINITION
RUN = xrun -R -l $(RUN_LOG) -sv_lib libcgra.so
else ifeq ($(TOOL), VCS)
COMPILE = $(VCS)
# COMPILE_RTL_ARGS += +nospecify
#RUN = ./simv +inst="'h4_8000_0400_0100_0040_0000" -lca -l $(RUN_LOG) +vcs+initmem+0 +vcs+initreg+0 -exitstatus
RUN = ./simv $(INST) $(NUM_INPUTS) -lca -l $(RUN_LOG) +vcs+initmem+0 +vcs+initreg+0 -exitstatus
else
@echo "TOOL must be either XCELIUM or VCS"
endif

ifeq ($(TOOL), XCELIUM)
DUMP_ARGS = -input unit_test_shm.tcl
else ifeq ($(TOOL), VCS)
DUMP_ARGS = -ucli -i dump_fsdb.tcl
endif

TEST_DIR ?= $(mkfile_dir)/TEST_DIR

.PHONY: compile
compile: COMPILE_ARGS = $(COMPILE_RTL_ARGS)
compile: INPUT_ARGS = $(DESIGN_FILES) $(TB_FILES) $(IP_FILES)
compile:
$(COMPILE)

.PHONY: run
run:
rm -f $(TEST_DIR)/OUTPUT_DIR/*
$(RUN) $(DUMP_ARGS)
# $(RUN) $(DUMP_ARGS) $(RUN_ARGS) $(APP_ARGS)

# -------------------------------------------------------------------
# GLS Compile
# -------------------------------------------------------------------
# compile testbench of garnet with xcelium
.PHONY: compile-gls
compile-gls: COMPILE_GLS_ARGS += +define+NON_STOP_IF_INPUT_Z
compile-gls: COMPILE_GLS_ARGS += +define+TSMC_CM_NO_WARNING
compile-gls: COMPILE_GLS_ARGS += +define+TSMC_CM_UNIT_DELAY
compile-gls: COMPILE_GLS_ARGS += +define+TSMC_INITIALIZE_MEM_USING_DEFAULT_TASKS
compile-gls: COMPILE_GLS_ARGS += +define+TSMC_MEM_LOAD_0
compile-gls: COMPILE_GLS_ARGS += -negdelay
compile-gls: COMPILE_ARGS = $(COMPILE_GLS_ARGS)
compile-gls: INPUT_ARGS = $(NETLIST_FILES) $(TB_FILES) $(IP_FILES)
compile-gls:
@rm -rf $(SDF_LOG); mkdir $(SDF_LOG)
$(COMPILE)


# -------------------------------------------------------------------
# Clean
# -------------------------------------------------------------------
.PHONY: clean
clean:
rm -rf xrun.log xrun.history xcelium.d simv simv.daidir csrc vcs.log cgra.shm cgra.fsdb sdf_stats.txt sdf_logs

.PHONY: sim
# sim: libcgra.so compile run
sim: clean compile run
7 changes: 7 additions & 0 deletions tests/dump_fsdb.tcl
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dump -file mu2f_io_core.fsdb -type FSDB
dump -add mu2f_io_core_tb -fsdb_opt +mda+packedmda+struct
power mu2f_io_core_tb.dut
power -enable
run
power -disable
run
161 changes: 161 additions & 0 deletions tests/mu2f_io_core_tb.sv
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`timescale 1ns/1ns



module mu2f_io_core_tb;

reg clk;
reg clk_en;
reg io2f_17_T0_ready;
reg io2f_17_T1_ready;
reg io2f_17_T2_ready;
reg io2f_17_T3_ready;
reg io2f_17_T4_ready;
reg [15:0] mu2io_16_0;
reg mu2io_16_0_valid;
reg [15:0] mu2io_16_1;
reg mu2io_16_1_valid;
reg [2:0] ready_select_0;
reg [2:0] ready_select_1;
reg rst_n;
reg tile_en;
reg [1:0] track_select_T0;
reg [1:0] track_select_T1;
reg [1:0] track_select_T2;
reg [1:0] track_select_T3;
reg [1:0] track_select_T4;

// wires for dut outputs
wire [16:0] io2f_17_T0;
wire io2f_17_T0_valid;
wire [16:0] io2f_17_T1;
wire io2f_17_T1_valid;
wire [16:0] io2f_17_T2;
wire io2f_17_T2_valid;
wire [16:0] io2f_17_T3;
wire io2f_17_T3_valid;
wire [16:0] io2f_17_T4;
wire io2f_17_T4_valid;
wire mu2io_16_0_ready;
wire mu2io_16_1_ready;

mu2f_io_core dut (
.clk(clk),
.clk_en(clk_en),
.io2f_17_T0_ready(io2f_17_T0_ready),
.io2f_17_T1_ready(io2f_17_T1_ready),
.io2f_17_T2_ready(io2f_17_T2_ready),
.io2f_17_T3_ready(io2f_17_T3_ready),
.io2f_17_T4_ready(io2f_17_T4_ready),
.mu2io_16_0(mu2io_16_0),
.mu2io_16_0_valid(mu2io_16_0_valid),
.mu2io_16_1(mu2io_16_1),
.mu2io_16_1_valid(mu2io_16_1_valid),
.ready_select_0(ready_select_0),
.ready_select_1(ready_select_1),
.rst_n(rst_n),
.tile_en(tile_en),
.track_select_T0(track_select_T0),
.track_select_T1(track_select_T1),
.track_select_T2(track_select_T2),
.track_select_T3(track_select_T3),
.track_select_T4(track_select_T4),
.io2f_17_T0(io2f_17_T0),
.io2f_17_T0_valid(io2f_17_T0_valid),
.io2f_17_T1(io2f_17_T1),
.io2f_17_T1_valid(io2f_17_T1_valid),
.io2f_17_T2(io2f_17_T2),
.io2f_17_T2_valid(io2f_17_T2_valid),
.io2f_17_T3(io2f_17_T3),
.io2f_17_T3_valid(io2f_17_T3_valid),
.io2f_17_T4(io2f_17_T4),
.io2f_17_T4_valid(io2f_17_T4_valid),
.mu2io_16_0_ready(mu2io_16_0_ready),
.mu2io_16_1_ready(mu2io_16_1_ready)

);

initial begin
clk = 0; // Initialize clock
forever begin
# 5 clk = ~clk;
end
end

initial begin
mu2io_16_0 = 0;
mu2io_16_1 = 6;

// toggle mu2io signals
forever begin
# 10
if (mu2io_16_0 < 4) begin
mu2io_16_0 += 1;
end else begin
mu2io_16_0 = 0;
end

if (mu2io_16_1 < 10) begin
mu2io_16_1 += 1;
end else begin
mu2io_16_1 = 6;
end

end
end


initial begin

clk_en = 1;
tile_en = 0;
rst_n = 0;
io2f_17_T0_ready = 1;
io2f_17_T1_ready = 1;
io2f_17_T2_ready = 1;
io2f_17_T3_ready = 1;
io2f_17_T4_ready = 1;

mu2io_16_0_valid = 1;
mu2io_16_1_valid = 1;

track_select_T0 = 2'b00;
track_select_T1 = 2'b00;
track_select_T2 = 2'b00;
track_select_T3 = 2'b00;
track_select_T4 = 2'b00;

ready_select_0 = 3'b000;
ready_select_1 = 3'b000;

// Release reset
#10 rst_n = 1;

// Apply input stimuli

// First test with tile_en OFF (mu inactive)
#15 track_select_T0 = 2'b01; track_select_T1 = 2'b10;
ready_select_0 = 3'b001; ready_select_1 = 3'b010;


// Now turn tile_en ON (mu active); testing track selects
#10 tile_en = 1;

#10 track_select_T1 = 2'b00; track_select_T2 = 2'b10;
#10 track_select_T2 = 2'b00; track_select_T3 = 2'b10;
#10 track_select_T3 = 2'b00; track_select_T4 = 2'b10;
#10 track_select_T4 = 2'b00;

#10 track_select_T0 = 2'b10; track_select_T1 = 2'b01;
#10 track_select_T1 = 2'b00; track_select_T2 = 2'b01;
#10 track_select_T2 = 2'b00; track_select_T3 = 2'b01;
#10 track_select_T3 = 2'b00; track_select_T4 = 2'b01;
#10 track_select_T4 = 2'b00; track_select_T0 = 2'b00;


// Finish simulation
#300 $finish;

end

endmodule

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