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ras_cas_gen.sch
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ras_cas_gen.sch
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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A3 16535 11693
encoding utf-8
Sheet 3 3
Title "Hannes256: C16/+4 256 kB RAM Expansion"
Date "2023-01-09"
Rev "2git"
Comp "SukkoPera"
Comment1 "Hannes Version (Update 1 with \"TED Feature\")"
Comment2 "Based on drawings by Solder/Synergy"
Comment3 "Licensed under CC BY-NC-SA 4.0"
Comment4 ""
$EndDescr
Text Notes 7600 2955 0 50 ~ 0
$FD16 WRITE
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Text Notes 15795 9665 2 50 ~ 0
Update 1 adds a "TED Feature": the purpose of the change is to restrict\nTED access to RAM bank 3 when the 6th bit of the RAM register is cleared.\nIf bit 6 is HIGH, the current ram bank is retained during TED access. So:\n- U5 Bit6=0: CPU accesses current RAM, TED always accesses RAM bank 3\n- U5 Bit6=1: CPU accesses current RAM, TED accesses current RAM
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Text Notes 5020 8135 0 50 ~ 0
THE 6529B IS HARD TO FIND THESE DAYS, SO A REPLACEMENT\nSHOULD BE FOUND. MANY CHIPS SEEM SUITABLE BUT THEY ALL\nLACK THE ABILITY TO PRESET THEIR OUTPUTS TO HIGH, WHICH\nIS ESSENTIAL FOR HOW THIS EXPANSION WORKS, SO WE MUST\nRESORT TO SOME TRICK...\n\nTHERE IS NO NEED FOR OPEN-COLLECTOR OUTPUTS.
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AR Path="/62E48B71/640F5993" Ref="#PWR?" Part="1"
AR Path="/63A22C28/640F5993" Ref="#PWR0102" Part="1"
F 0 "#PWR0102" H 7255 2480 50 0001 C CNN
F 1 "+5V" H 7270 2803 50 0000 C CNN
F 2 "" H 7255 2630 50 0001 C CNN
F 3 "" H 7255 2630 50 0001 C CNN
1 7255 2630
1 0 0 -1
$EndComp
Wire Wire Line
7255 2760 7255 2630
Wire Wire Line
7105 2760 7255 2760
Wire Wire Line
5475 3860 5475 3975
Wire Wire Line
5605 3860 5475 3860
Wire Wire Line
5550 3160 5605 3160
Entry Wire Line
5090 3460 5190 3560
Entry Wire Line
5090 3360 5190 3460
Entry Wire Line
5090 3260 5190 3360
Entry Wire Line
5090 3160 5190 3260
Text Label 5190 3460 0 50 ~ 0
a14
Wire Wire Line
5605 3460 5190 3460
Text Label 5190 3360 0 50 ~ 0
a13
Wire Wire Line
5605 3360 5190 3360
Text Label 5190 3260 0 50 ~ 0
a12
Wire Wire Line
5605 3260 5190 3260
Text Label 5190 3560 0 50 ~ 0
a15
Wire Wire Line
5605 3560 5190 3560
Entry Wire Line
5090 2960 5190 3060
$Comp
L GAL20V8:GAL20V8 U2
U 1 1 63F7FBC6
P 6355 3310
F 0 "U2" H 6355 4225 50 0000 C CNN
F 1 "GAL20V8" H 6355 4134 50 0000 C CNN
F 2 "Package_DIP:DIP-24_W7.62mm_Socket" H 6355 3310 50 0001 C CNN
F 3 "DOCUMENTATION" H 6355 3310 50 0001 C CNN
1 6355 3310
1 0 0 -1
$EndComp
Text GLabel 7210 3060 2 50 Output ~ 0
~CS_OUT
Text GLabel 5550 3160 0 50 Input ~ 0
~CS_IN
Wire Bus Line
4535 2250 5090 2250
Entry Wire Line
5090 2860 5190 2960
Entry Wire Line
5090 2760 5190 2860
Entry Wire Line
5090 2660 5190 2760
Text GLabel 4535 2250 0 50 Input ~ 0
a[0..15]
$Comp
L power:GND #PWR?
U 1 1 63A644D4
P 5475 3975
AR Path="/63A644D4" Ref="#PWR?" Part="1"
AR Path="/62E48B71/63A644D4" Ref="#PWR?" Part="1"
AR Path="/63A22C28/63A644D4" Ref="#PWR015" Part="1"
F 0 "#PWR015" H 5475 3725 50 0001 C CNN
F 1 "GND" H 5480 3802 50 0000 C CNN
F 2 "" H 5475 3975 50 0001 C CNN
F 3 "" H 5475 3975 50 0001 C CNN
1 5475 3975
1 0 0 -1
$EndComp
Wire Wire Line
7105 3060 7210 3060
Text Label 5190 2960 0 50 ~ 0
a2
Wire Wire Line
5605 2960 5190 2960
Text Label 5190 2860 0 50 ~ 0
a1
Wire Wire Line
5605 2860 5190 2860
Text Label 5190 2760 0 50 ~ 0
a0
Wire Wire Line
5605 2760 5190 2760
Text Label 5190 3060 0 50 ~ 0
a3
Wire Wire Line
5605 3060 5190 3060
Text Label 12485 5855 0 60 ~ 0
m8
Entry Wire Line
13035 5755 12935 5855
Wire Wire Line
7105 3160 9570 3160
Wire Wire Line
9570 3160 9570 5855
Wire Wire Line
9570 5855 12935 5855
Wire Wire Line
5190 3760 5605 3760
Wire Wire Line
7490 3860 7105 3860
Wire Wire Line
7105 3760 7490 3760
Wire Wire Line
7105 3660 7490 3660
Wire Wire Line
7105 2960 7490 2960
Text Notes 5730 4270 0 50 ~ 0
ALL THE GLUE LOGIC WAS REPLACED\nWITH A SINGLE OLD-SKOOLZ GAL!
$Comp
L power:+5V #PWR?
U 1 1 633D8DCD
P 4415 2960
AR Path="/633D8DCD" Ref="#PWR?" Part="1"
AR Path="/62E48B71/633D8DCD" Ref="#PWR?" Part="1"
AR Path="/63A22C28/633D8DCD" Ref="#PWR0106" Part="1"
F 0 "#PWR0106" H 4415 2810 50 0001 C CNN
F 1 "+5V" H 4430 3133 50 0000 C CNN
F 2 "" H 4415 2960 50 0001 C CNN
F 3 "" H 4415 2960 50 0001 C CNN
1 4415 2960
1 0 0 -1
$EndComp
$Comp
L power:+5V #PWR?
U 1 1 633D9554
P 13485 4405
AR Path="/633D9554" Ref="#PWR?" Part="1"
AR Path="/62E48B71/633D9554" Ref="#PWR?" Part="1"
AR Path="/63A22C28/633D9554" Ref="#PWR0107" Part="1"
F 0 "#PWR0107" H 13485 4255 50 0001 C CNN
F 1 "+5V" H 13500 4578 50 0000 C CNN
F 2 "" H 13485 4405 50 0001 C CNN
F 3 "" H 13485 4405 50 0001 C CNN
1 13485 4405
1 0 0 -1
$EndComp
$Comp
L power:+5V #PWR?
U 1 1 633E34D2
P 13485 3790
AR Path="/633E34D2" Ref="#PWR?" Part="1"
AR Path="/62E48B71/633E34D2" Ref="#PWR?" Part="1"
AR Path="/63A22C28/633E34D2" Ref="#PWR0108" Part="1"
F 0 "#PWR0108" H 13485 3640 50 0001 C CNN
F 1 "+5V" H 13500 3963 50 0000 C CNN
F 2 "" H 13485 3790 50 0001 C CNN
F 3 "" H 13485 3790 50 0001 C CNN
1 13485 3790
1 0 0 -1
$EndComp
$Comp
L power:VCC #PWR0109
U 1 1 633E54A0
P 13855 3790
F 0 "#PWR0109" H 13855 3640 50 0001 C CNN
F 1 "VCC" H 13870 3963 50 0000 C CNN
F 2 "" H 13855 3790 50 0001 C CNN
F 3 "" H 13855 3790 50 0001 C CNN
1 13855 3790
1 0 0 -1
$EndComp
Wire Wire Line
13855 3790 13855 3890
Wire Wire Line
13855 3890 13485 3890
Wire Wire Line
13485 3890 13485 3790
Text Notes 11270 3905 0 50 ~ 0
'157s WILL BE FINE, TOO
Wire Wire Line
7105 2860 7345 2860
Wire Wire Line
7345 2860 7345 2760
Wire Wire Line
7345 2760 7585 2760
Text GLabel 7585 2760 2 50 Input ~ 0
R_~W
Text Notes 7850 2815 0 50 ~ 0
R/~W~ WAS NOT USED IN THE ORIGINAL\nHANNES/SOLDER CIRCUIT BUT WE NEED IT\nIN ORDER TO KNOW WHETHER TO ENABLE\nTHE 74x74 OR THE 74x245.
Text Label 12340 7695 2 50 ~ 0
d7
Entry Wire Line
12440 7795 12340 7695
Wire Bus Line
12440 7795 12970 7795
Text GLabel 12970 7795 2 50 Output ~ 0
d[0..7]
Wire Wire Line
12340 7695 12075 7695
Wire Wire Line
12075 6995 12340 6995
Wire Wire Line
12075 7095 12340 7095
Wire Wire Line
12075 7195 12340 7195
Wire Wire Line
12075 7295 12340 7295
Wire Wire Line
12075 7395 12340 7395
Wire Wire Line
12075 7495 12340 7495
Wire Wire Line
12075 7595 12340 7595
Text Label 12340 6995 2 50 ~ 0
d0
Text Label 12340 7095 2 50 ~ 0
d1
Text Label 12340 7195 2 50 ~ 0
d2
Text Label 12340 7295 2 50 ~ 0
d3
Text Label 12340 7395 2 50 ~ 0
d4
Text Label 12340 7495 2 50 ~ 0
d5
Text Label 12340 7595 2 50 ~ 0
d6
Entry Wire Line
12440 7195 12340 7095
Entry Wire Line
12440 7295 12340 7195
Entry Wire Line
12440 7395 12340 7295
Entry Wire Line
12440 7495 12340 7395
Entry Wire Line
12440 7595 12340 7495
Entry Wire Line
12440 7695 12340 7595
Entry Wire Line
12440 7095 12340 6995
Text Label 10560 6995 0 50 ~ 0
p0
Text Label 10560 7095 0 50 ~ 0
p1
Text Label 10560 7595 0 50 ~ 0
p6
Text Label 10560 7695 0 50 ~ 0
p7
Wire Wire Line
11575 6610 11575 6650
$Comp
L power:+5V #PWR?
U 1 1 637951AE
P 11575 6610
AR Path="/637951AE" Ref="#PWR?" Part="1"
AR Path="/62E48B71/637951AE" Ref="#PWR?" Part="1"
AR Path="/63A22C28/637951AE" Ref="#PWR0112" Part="1"
F 0 "#PWR0112" H 11575 6460 50 0001 C CNN
F 1 "+5V" H 11590 6783 50 0000 C CNN
F 2 "" H 11575 6610 50 0001 C CNN
F 3 "" H 11575 6610 50 0001 C CNN
1 11575 6610
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 63795E43
P 11575 8380
AR Path="/63795E43" Ref="#PWR?" Part="1"
AR Path="/62E48B71/63795E43" Ref="#PWR?" Part="1"
AR Path="/63A22C28/63795E43" Ref="#PWR0114" Part="1"
F 0 "#PWR0114" H 11575 8130 50 0001 C CNN
F 1 "GND" H 11580 8207 50 0000 C CNN
F 2 "" H 11575 8380 50 0001 C CNN
F 3 "" H 11575 8380 50 0001 C CNN
1 11575 8380
1 0 0 -1
$EndComp
Wire Wire Line
7105 3260 7490 3260
Text Label 7490 3260 2 50 ~ 0
~cs_ramrd
Text Label 10560 7995 0 50 ~ 0
~cs_ramrd
Text Notes 10595 9015 0 50 ~ 0
WE ALSO NEED SOMETHING ELSE TO ALLOW OUR\nRAM CONTROL REGISTER TO BE READ BACK. SINCE\nWE ARE WORKING WITH REVERSE LOGIC, WE USE\nAN INVERTING BUFFER AND... TA-DA!
Text Notes 6085 2300 0 50 ~ 0
GAL22V10 CAN BE\nUSED AS WELL
Text Notes 7600 3260 0 50 ~ 0
$FD16 READ
Wire Wire Line
11075 7595 10560 7595
Wire Wire Line
11075 7695 10560 7695
Wire Wire Line
11075 6995 10560 6995
Wire Wire Line
11075 7095 10560 7095
Text Label 10560 7195 0 50 ~ 0
p2
Text Label 10560 7295 0 50 ~ 0
p3
Wire Wire Line
11075 7195 10560 7195
Wire Wire Line
11075 7295 10560 7295
Text Label 10560 7395 0 50 ~ 0
p4
Text Label 10560 7495 0 50 ~ 0
p5
Wire Wire Line
11075 7395 10560 7395
Wire Wire Line
11075 7495 10560 7495
Wire Wire Line
6055 5465 6055 5375
$Comp
L power:+5V #PWR?
U 1 1 6399FCCB
P 6055 5375
AR Path="/6399FCCB" Ref="#PWR?" Part="1"
AR Path="/62E48B71/6399FCCB" Ref="#PWR?" Part="1"
AR Path="/63A22C28/6399FCCB" Ref="#PWR0113" Part="1"
F 0 "#PWR0113" H 6055 5225 50 0001 C CNN
F 1 "+5V" H 6070 5548 50 0000 C CNN
F 2 "" H 6055 5375 50 0001 C CNN
F 3 "" H 6055 5375 50 0001 C CNN
1 6055 5375
1 0 0 -1
$EndComp
Wire Wire Line
6055 7160 6055 7065
$Comp
L power:GND #PWR?
U 1 1 639A0F2B
P 6055 7160
AR Path="/639A0F2B" Ref="#PWR?" Part="1"
AR Path="/62E48B71/639A0F2B" Ref="#PWR?" Part="1"
AR Path="/63A22C28/639A0F2B" Ref="#PWR0116" Part="1"
F 0 "#PWR0116" H 6055 6910 50 0001 C CNN
F 1 "GND" H 6060 6987 50 0000 C CNN
F 2 "" H 6055 7160 50 0001 C CNN
F 3 "" H 6055 7160 50 0001 C CNN
1 6055 7160
1 0 0 -1
$EndComp
Text Label 5095 6665 0 50 ~ 0
cs_ramwr
Wire Wire Line
5090 5765 5555 5765
Entry Wire Line
4990 5865 5090 5765
Text Label 5090 5765 0 50 ~ 0
d0
Wire Wire Line
5090 5965 5555 5965
Entry Wire Line
4990 6065 5090 5965
Text Label 5090 5965 0 50 ~ 0
d2
Wire Wire Line
5090 6165 5555 6165
Entry Wire Line
4990 6265 5090 6165
Text Label 5090 6165 0 50 ~ 0
d4
Wire Wire Line
5090 6365 5555 6365
Entry Wire Line
4990 6465 5090 6365
Text Label 5090 6365 0 50 ~ 0
d6
Wire Wire Line
5090 5865 5555 5865
Entry Wire Line
4990 5965 5090 5865
Text Label 5095 5865 0 50 ~ 0
d1
Wire Wire Line
5090 6065 5555 6065
Entry Wire Line
4990 6165 5090 6065
Text Label 5095 6065 0 50 ~ 0
d3
Wire Wire Line
5090 6265 5555 6265
Entry Wire Line
4990 6365 5090 6265
Text Label 5095 6265 0 50 ~ 0
d5
Wire Wire Line
5090 6465 5555 6465
Text GLabel 4620 6565 0 50 Input ~ 0
d[0..7]
Entry Wire Line
4990 6565 5090 6465
Text Label 5095 6465 0 50 ~ 0
d7
Wire Wire Line
6555 5765 6660 5765
Entry Wire Line
7825 5765 7925 5865
Wire Wire Line
6555 5965 6860 5965
Entry Wire Line
7825 5965 7925 6065
Wire Wire Line
6555 6165 7275 6165
Entry Wire Line
7825 6165 7925 6265
Wire Wire Line
6555 6365 7475 6365
Entry Wire Line
7825 6365 7925 6465
Wire Wire Line
6555 5865 6760 5865
Entry Wire Line
7825 5865 7925 5965
Wire Wire Line
6555 6065 6960 6065
Entry Wire Line
7825 6065 7925 6165
Wire Wire Line
6555 6265 7375 6265
Entry Wire Line
7825 6265 7925 6365
Wire Bus Line
7925 6565 8255 6565
Wire Bus Line
4620 6565 4990 6565
Text GLabel 8255 6565 2 50 Output ~ 0
p[0..7]
Text Label 7825 5765 2 50 ~ 0
p0
Text Label 7825 5965 2 50 ~ 0
p2
Text Label 7825 6165 2 50 ~ 0
p4
Text Label 7825 6365 2 50 ~ 0
p6
Text Label 7825 5865 2 50 ~ 0
p1
Text Label 7825 6065 2 50 ~ 0
p3
Text Label 7825 6265 2 50 ~ 0
p5
Text Label 7825 6465 2 50 ~ 0
p7
Text Label 7490 3860 2 50 ~ 0
p1
Text Label 5190 3760 0 50 ~ 0
p0
Text Label 7490 3760 2 50 ~ 0
p6
Text Label 7490 3660 2 50 ~ 0
p7
Entry Wire Line
7490 3660 7590 3760
Entry Wire Line
7490 3760 7590 3860
Entry Wire Line
7490 3860 7590 3960
Entry Wire Line
5190 3760 5090 3860
Wire Bus Line
5090 3860 5090 4535
Wire Bus Line
5090 4535 7590 4535
Wire Bus Line
4540 4535 5090 4535
Text GLabel 4540 4535 0 50 Input ~ 0
~p~[0..7]
Connection ~ 5090 4535
Wire Bus Line
5090 4535 5095 4535
Text Notes 7600 3490 0 50 ~ 0
INTERMEDIATE SIGNAL TO WORKAROUND\nGAL LIMITATIONS - LEAVE UNCONNECTED
Wire Wire Line
7105 3460 7490 3460
NoConn ~ 7490 3460
Wire Wire Line
4590 5430 4590 5635
Wire Wire Line
4590 5935 4590 6120
Wire Wire Line
6555 6465 7575 6465
Entry Wire Line
7825 6465 7925 6565
$Comp
L 74xx:74LS573 U3
U 1 1 63DD8844
P 6055 6265
F 0 "U3" H 6255 6915 50 0000 C CNN
F 1 "74HCT573" H 6315 5585 50 0000 C CNN
F 2 "Package_SO:SO-20_5.3x12.6mm_P1.27mm" H 6055 6265 50 0001 C CNN
F 3 "74xx/74hc573.pdf" H 6055 6265 50 0001 C CNN
F 4 "595-SN74HCT573NSR" H 6055 6265 50 0001 C CNN "MouserPN"
F 5 "C2864941" H 6055 6265 50 0001 C CNN "LCSC"
1 6055 6265
1 0 0 -1
$EndComp
Text Label 5095 6765 0 50 ~ 0
~u3enable
$Comp
L Timer:NE555D U15
U 1 1 63DF3FB7
P 3520 7350
F 0 "U15" H 3770 7705 50 0000 C CNN
F 1 "NE555" H 3735 6990 50 0000 C CNN
F 2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" H 4370 6950 50 0001 C CNN
F 3 "http://www.ti.com/lit/ds/symlink/ne555.pdf" H 4370 6950 50 0001 C CNN
F 4 "C5125085" H 3520 7350 50 0001 C CNN "LCSC"
1 3520 7350
1 0 0 -1
$EndComp
Wire Wire Line
3520 6950 3520 6860
$Comp
L power:+5V #PWR?
U 1 1 63DF5EBC
P 3520 6860
AR Path="/63DF5EBC" Ref="#PWR?" Part="1"
AR Path="/62E48B71/63DF5EBC" Ref="#PWR?" Part="1"
AR Path="/63A22C28/63DF5EBC" Ref="#PWR028" Part="1"
F 0 "#PWR028" H 3520 6710 50 0001 C CNN
F 1 "+5V" H 3535 7033 50 0000 C CNN
F 2 "" H 3520 6860 50 0001 C CNN
F 3 "" H 3520 6860 50 0001 C CNN
1 3520 6860
1 0 0 -1
$EndComp
Wire Wire Line
3520 8170 3520 8070
$Comp
L power:GND #PWR?
U 1 1 63DFD090
P 3520 8170
AR Path="/63DFD090" Ref="#PWR?" Part="1"
AR Path="/62E48B71/63DFD090" Ref="#PWR?" Part="1"
AR Path="/63A22C28/63DFD090" Ref="#PWR029" Part="1"
F 0 "#PWR029" H 3520 7920 50 0001 C CNN
F 1 "GND" H 3525 7997 50 0000 C CNN
F 2 "" H 3520 8170 50 0001 C CNN
F 3 "" H 3520 8170 50 0001 C CNN
1 3520 8170
1 0 0 -1
$EndComp
$Comp
L Device:C C16
U 1 1 63E09791
P 2905 7825
F 0 "C16" H 2790 7871 50 0000 R CNN
F 1 "10n" H 2790 7780 50 0000 R CNN
F 2 "Capacitor_SMD:C_0805_2012Metric_Pad1.18x1.45mm_HandSolder" H 2943 7675 50 0001 C CNN
F 3 "~" H 2905 7825 50 0001 C CNN
F 4 "C1710" H 2905 7825 50 0001 C CNN "LCSC"
1 2905 7825
1 0 0 -1
$EndComp
Wire Wire Line
2905 7975 2905 8070
Wire Wire Line
2905 8070 3520 8070
Connection ~ 3520 8070