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ReVox.kicad_pcb
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(kicad_pcb (version 20171130) (host pcbnew 5.1.12)
(general
(thickness 1.6)
(drawings 42)
(tracks 317)
(zones 0)
(modules 40)
(nets 77)
)
(page A4)
(title_block
(title ReVox)
(date 2023-12-20)
(rev 1git)
(company SukkoPera)
(comment 1 "Based on work by Yeo Kheng Meng")
(comment 2 "Licensed under CC BY-NC-SA 4.0")
)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user hide)
(42 Eco1.User user hide)
(43 Eco2.User user hide)
(44 Edge.Cuts user)
(45 Margin user hide)
(46 B.CrtYd user hide)
(47 F.CrtYd user hide)
(49 F.Fab user hide)
)
(setup
(last_trace_width 0.25)
(trace_clearance 0.2)
(zone_clearance 0.254)
(zone_45_only yes)
(trace_min 0.2)
(via_size 0.6)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(edge_width 0.05)
(segment_width 0.2)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.12)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.6 1.6)
(pad_drill 0.8)
(pad_to_mask_clearance 0)
(aux_axis_origin 121.793 148.082)
(grid_origin 121.793 148.082)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x010f0_ffffffff)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory "gerbers"))
)
(net 0 "")
(net 1 GND)
(net 2 +5V)
(net 3 /d7)
(net 4 /d6)
(net 5 /d4)
(net 6 /d5)
(net 7 /d3)
(net 8 /d2)
(net 9 /d1)
(net 10 /d0)
(net 11 /r_~w)
(net 12 /phi2)
(net 13 /~reset)
(net 14 /a15)
(net 15 /a14)
(net 16 /a13)
(net 17 /a12)
(net 18 /a11)
(net 19 /a10)
(net 20 /a9)
(net 21 /a8)
(net 22 /a7)
(net 23 /a6)
(net 24 /a5)
(net 25 /a4)
(net 26 /a1)
(net 27 /a0)
(net 28 /a3)
(net 29 /a2)
(net 30 /analog_audio)
(net 31 /amplified_audio)
(net 32 /ext_audio)
(net 33 /b0)
(net 34 "Net-(R1-Pad2)")
(net 35 "Net-(R3-Pad1)")
(net 36 /b1)
(net 37 "Net-(R5-Pad1)")
(net 38 /b2)
(net 39 "Net-(R7-Pad1)")
(net 40 /b3)
(net 41 "Net-(R10-Pad2)")
(net 42 /b4)
(net 43 "Net-(R11-Pad1)")
(net 44 /b5)
(net 45 "Net-(R13-Pad1)")
(net 46 /b6)
(net 47 /b7)
(net 48 /amplifier_in)
(net 49 /latch_clear)
(net 50 /latch_clk)
(net 51 "Net-(CN2-PadRN)")
(net 52 VCOM)
(net 53 "Net-(CN1-PadBB)")
(net 54 "Net-(CN1-PadAA)")
(net 55 "Net-(CN1-PadZ)")
(net 56 "Net-(CN1-PadE)")
(net 57 "Net-(CN1-PadD)")
(net 58 "Net-(CN1-PadB)")
(net 59 "Net-(CN1-Pad4)")
(net 60 "Net-(CN1-Pad22)")
(net 61 "Net-(CN1-Pad13)")
(net 62 "Net-(CN1-Pad12)")
(net 63 "Net-(CN1-Pad11)")
(net 64 "Net-(CN1-Pad10)")
(net 65 "Net-(CN1-Pad9)")
(net 66 "Net-(CN1-Pad8)")
(net 67 "Net-(CN1-Pad7)")
(net 68 "Net-(CN1-Pad6)")
(net 69 "Net-(R19-Pad1)")
(net 70 "Net-(R20-Pad1)")
(net 71 "Net-(R21-Pad1)")
(net 72 "Net-(R21-Pad2)")
(net 73 "Net-(RV1-Pad3)")
(net 74 "Net-(U1-Pad13)")
(net 75 "Net-(C3-Pad2)")
(net 76 "Net-(C5-Pad1)")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net /a0)
(add_net /a1)
(add_net /a10)
(add_net /a11)
(add_net /a12)
(add_net /a13)
(add_net /a14)
(add_net /a15)
(add_net /a2)
(add_net /a3)
(add_net /a4)
(add_net /a5)
(add_net /a6)
(add_net /a7)
(add_net /a8)
(add_net /a9)
(add_net /amplified_audio)
(add_net /amplifier_in)
(add_net /analog_audio)
(add_net /b0)
(add_net /b1)
(add_net /b2)
(add_net /b3)
(add_net /b4)
(add_net /b5)
(add_net /b6)
(add_net /b7)
(add_net /d0)
(add_net /d1)
(add_net /d2)
(add_net /d3)
(add_net /d4)
(add_net /d5)
(add_net /d6)
(add_net /d7)
(add_net /ext_audio)
(add_net /latch_clear)
(add_net /latch_clk)
(add_net /phi2)
(add_net /r_~w)
(add_net /~reset)
(add_net "Net-(C3-Pad2)")
(add_net "Net-(C5-Pad1)")
(add_net "Net-(CN1-Pad10)")
(add_net "Net-(CN1-Pad11)")
(add_net "Net-(CN1-Pad12)")
(add_net "Net-(CN1-Pad13)")
(add_net "Net-(CN1-Pad22)")
(add_net "Net-(CN1-Pad4)")
(add_net "Net-(CN1-Pad6)")
(add_net "Net-(CN1-Pad7)")
(add_net "Net-(CN1-Pad8)")
(add_net "Net-(CN1-Pad9)")
(add_net "Net-(CN1-PadAA)")
(add_net "Net-(CN1-PadB)")
(add_net "Net-(CN1-PadBB)")
(add_net "Net-(CN1-PadD)")
(add_net "Net-(CN1-PadE)")
(add_net "Net-(CN1-PadZ)")
(add_net "Net-(CN2-PadRN)")
(add_net "Net-(R1-Pad2)")
(add_net "Net-(R10-Pad2)")
(add_net "Net-(R11-Pad1)")
(add_net "Net-(R13-Pad1)")
(add_net "Net-(R19-Pad1)")
(add_net "Net-(R20-Pad1)")
(add_net "Net-(R21-Pad1)")
(add_net "Net-(R21-Pad2)")
(add_net "Net-(R3-Pad1)")
(add_net "Net-(R5-Pad1)")
(add_net "Net-(R7-Pad1)")
(add_net "Net-(RV1-Pad3)")
(add_net "Net-(U1-Pad13)")
)
(net_class Power ""
(clearance 0.2)
(trace_width 0.5)
(via_dia 0.8)
(via_drill 0.6)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net +5V)
(add_net GND)
(add_net VCOM)
)
(module ReVox:C16_Cart_Conn locked (layer F.Cu) (tedit 6517447E) (tstamp 6312E1E6)
(at 152.177 143.764)
(path /64651B19)
(zone_connect 2)
(fp_text reference CN1 (at 0 5) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value EXPANSION_PORT (at 0 6.5) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -26 4) (end 26 4) (layer Dwgs.User) (width 0.15))
(fp_line (start -26 -28) (end -26 4) (layer Dwgs.User) (width 0.15))
(fp_line (start 26 -28) (end -26 -28) (layer Dwgs.User) (width 0.15))
(fp_line (start 26 4) (end 26 -28) (layer Dwgs.User) (width 0.15))
(fp_text user "This is exactly the size that will fit INTO your C16" (at 0 -29.464) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd custom (at -24 0) (size 0.9 7.2) (layers F.Cu)
(net 1 GND) (zone_connect 2)
(options (clearance outline) (anchor rect))
(primitives
(gr_poly (pts
(xy 0.632 -2) (xy 0.632 1.524) (xy 0.378 3.429) (xy -0.384 3.429) (xy -0.638 1.524)
(xy -0.638 -2) (xy -0.384 -2.921) (xy 0.378 -2.921)) (width 0.1))
))
(pad 3 smd custom (at -20 0) (size 0.9 7.2) (layers F.Cu)
(net 2 +5V) (zone_connect 2)
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(primitives
(gr_poly (pts
(xy 0.632 -2) (xy 0.632 1.524) (xy 0.378 3.429) (xy -0.384 3.429) (xy -0.638 1.524)
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))
(pad CC smd custom (at 24 0) (size 0.9 7.2) (layers B.Cu)
(net 1 GND) (zone_connect 2)
(options (clearance outline) (anchor rect))
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))
(pad BB smd custom (at 22 0) (size 0.9 7.2) (layers B.Cu)
(net 53 "Net-(CN1-PadBB)") (zone_connect 2)
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))
(pad AA smd custom (at 20 0) (size 0.9 7.2) (layers B.Cu)
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))
(pad Z smd custom (at 18 0) (size 0.9 7.2) (layers B.Cu)
(net 55 "Net-(CN1-PadZ)") (zone_connect 2)
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(gr_poly (pts
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))
(pad Y smd custom (at 16 0) (size 0.9 7.2) (layers B.Cu)
(net 27 /a0) (zone_connect 2)
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(xy 0.632 -2) (xy 0.632 1.524) (xy 0.378 3.429) (xy -0.384 3.429) (xy -0.638 1.524)
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))
(pad X smd custom (at 14 0) (size 0.9 7.2) (layers B.Cu)
(net 26 /a1) (zone_connect 2)
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(pad W smd custom (at 12 0) (size 0.9 7.2) (layers B.Cu)
(net 29 /a2) (zone_connect 2)
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))
(pad V smd custom (at 10 0) (size 0.9 7.2) (layers B.Cu)
(net 28 /a3) (zone_connect 2)
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))
(pad U smd custom (at 8 0) (size 0.9 7.2) (layers B.Cu)
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(module ReVox:AudioJack_SJ1-3525N (layer F.Cu) (tedit 623753B6) (tstamp 6429AA3F)
(at 174.411 66.374 180)
(tags "audio jack 3.5mm trs")
(path /6525CFF2)
(fp_text reference CN2 (at 0 -8.664999 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value RAW_OUT (at 0 -8.8) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 2 4.5) (end 7.4 4.5) (layer Dwgs.User) (width 0.12))
(fp_line (start 2 3.3) (end 2 4.5) (layer Dwgs.User) (width 0.15))
(fp_line (start -2 4.5) (end -2 3.3) (layer Dwgs.User) (width 0.15))
(fp_line (start -2 3.3) (end 2 3.3) (layer Dwgs.User) (width 0.15))
(fp_line (start -6 -7.5) (end 6 -7.5) (layer F.SilkS) (width 0.15))
(fp_line (start -4.5 4.5) (end -2 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 6 3.5) (end 6 -7.5) (layer F.SilkS) (width 0.15))
(fp_line (start -6 3.5) (end -6 -7.5) (layer F.SilkS) (width 0.15))
(fp_line (start -4.5 4.5) (end -4.5 3.5) (layer F.SilkS) (width 0.15))
(fp_line (start -4.5 3.5) (end -6 3.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2 4.5) (end -2 3.3) (layer F.SilkS) (width 0.15))
(fp_line (start -2 3.3) (end 2 3.3) (layer F.SilkS) (width 0.15))
(fp_line (start 2 3.3) (end 2 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 2 4.5) (end 4.5 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 4.5 4.5) (end 4.5 3.5) (layer F.SilkS) (width 0.15))
(fp_line (start 6 3.5) (end 4.5 3.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2 4.5) (end -7.4 4.5) (layer Dwgs.User) (width 0.12))
(fp_text user "PCB EDGE" (at -11.8 4.5) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad S thru_hole oval (at 0 0 180) (size 2.2 1.5) (drill oval 1.5 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad "" np_thru_hole circle (at -5 0 180) (size 1.2 1.2) (drill 1.2) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -5 2.5 180) (size 1.2 1.2) (drill 1.2) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 5 0 180) (size 1.2 1.2) (drill 1.2) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 5 2.5 180) (size 1.2 1.2) (drill 1.2) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 0 -5 180) (size 1.2 1.2) (drill 1.2) (layers *.Cu *.Mask))
(pad RN thru_hole oval (at -2.5 -5 180) (size 1.5 2.2) (drill oval 0.8 1.5) (layers *.Cu *.Mask)
(net 51 "Net-(CN2-PadRN)"))
(pad R thru_hole oval (at -5 -5 180) (size 1.5 2.2) (drill oval 0.8 1.5) (layers *.Cu *.Mask)
(net 30 /analog_audio))
(pad TN thru_hole oval (at 2.5 -5 180) (size 1.5 2.2) (drill oval 0.8 1.5) (layers *.Cu *.Mask)
(net 48 /amplifier_in))
(pad T thru_hole oval (at 5 -5 180) (size 1.5 2.2) (drill oval 0.8 1.5) (layers *.Cu *.Mask)
(net 30 /analog_audio))
(model ${KIPRJMOD}/3dModels/sj1-3525n.x3d
(offset (xyz 0 1.5 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 -90))
)
)
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 64F697C7)
(at 140.97 79.375 270)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /65C5C654)
(fp_text reference R22 (at -1.778 0 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100k (at 5.08 0.0675 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
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(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
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(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
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(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 5.08 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 76 "Net-(C5-Pad1)"))
(pad 2 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 72 "Net-(R21-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_DIP:DIP-8_W7.62mm_Socket_LongPads (layer F.Cu) (tedit 5A02E8C5) (tstamp 64F65C0A)
(at 134.27075 107.315 270)
(descr "8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads")
(path /65C5C5F8)
(fp_text reference U3 (at 7.62 10.44575 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TLC272 (at 3.8675 3.8 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 9.15 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.15 9.2) (end 9.15 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 9.2) (end 9.15 9.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 -1.6) (end -1.55 9.2) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.06 -1.39) (end -1.44 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 9.06 9.01) (end 9.06 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 9.01) (end 9.06 9.01) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 -1.39) (end -1.44 9.01) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 8.95) (end 6.06 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 8.95) (end 6.06 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 -1.33) (end 1.56 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.56 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 8.89 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 8.89 8.95) (end 8.89 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 8.95) (end 8.89 8.95) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.33) (end -1.27 8.95) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 8.89) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 8.89) (end 0.635 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_text user %R (at 3.81 3.81 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(pad 8 thru_hole oval (at 7.62 0 270) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +5V))
(pad 4 thru_hole oval (at 0 7.62 270) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad 7 thru_hole oval (at 7.62 2.54 270) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 71 "Net-(R21-Pad1)"))
(pad 3 thru_hole oval (at 0 5.08 270) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 52 VCOM))
(pad 6 thru_hole oval (at 7.62 5.08 270) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 69 "Net-(R19-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54 270) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 72 "Net-(R21-Pad2)"))
(pad 5 thru_hole oval (at 7.62 7.62 270) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 52 VCOM))
(pad 1 thru_hole rect (at 0 0 270) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 76 "Net-(C5-Pad1)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-8_W7.62mm_Socket.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-8_W7.62mm.wrl
(offset (xyz 0 0 4))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D7.0mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 6429A9DF) (tstamp 64294006)
(at 134.27075 118.745 180)
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=7*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 7mm width 2.5mm Capacitor")
(path /64B83085)
(fp_text reference C7 (at 7.52475 0.0675) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 2.5 0.0675) (layer F.SilkS)
(effects (font (size 1 0.8) (thickness 0.15)))
)
(fp_line (start 6.25 -1.5) (end -1.25 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.25 1.5) (end 6.25 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 1.5) (end 6.25 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 -1.5) (end -1.25 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.12 -1.37) (end 6.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.12 -1.37) (end -1.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.12 1.37) (end 6.12 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.12 -1.37) (end 6.12 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6 -1.25) (end -1 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6 1.25) (end 6 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1 1.25) (end 6 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1 -1.25) (end -1 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 2.5 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 +5V))
(pad 2 thru_hole circle (at 5 0 225) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D7.0mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:CP_Radial_D6.3mm_P2.50mm (layer F.Cu) (tedit 64CBE29B) (tstamp 64293FF3)
(at 134.27075 123.825 180)
(descr "CP, Radial series, Radial, pin pitch=2.50mm, , diameter=6.3mm, Electrolytic Capacitor")
(tags "CP Radial series Radial pin pitch 2.50mm diameter 6.3mm Electrolytic Capacitor")
(path /64C59A52)
(fp_text reference C6 (at 1.18238 -4.318) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100u (at -0.127 1.397) (layer F.SilkS)
(effects (font (size 0.8 0.7) (thickness 0.12)))
)
(fp_circle (center 1.25 0) (end 4.4 0) (layer F.Fab) (width 0.1))
(fp_circle (center 1.25 0) (end 4.52 0) (layer F.SilkS) (width 0.12))
(fp_circle (center 1.25 0) (end 4.65 0) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.443972 -1.3735) (end -0.813972 -1.3735) (layer F.Fab) (width 0.1))
(fp_line (start -1.128972 -1.6885) (end -1.128972 -1.0585) (layer F.Fab) (width 0.1))
(fp_line (start 1.25 -3.23) (end 1.25 3.23) (layer F.SilkS) (width 0.12))
(fp_line (start 1.29 -3.23) (end 1.29 3.23) (layer F.SilkS) (width 0.12))
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