SCOAP Analysis Tool: Developed a tool which performs SCOAP analysis of digital circuit test-ability. Starting from a HDL(verilog) description of a circuit, Generating its gate level netlist, Parsing the same to obtain the controllability and observability values at every wire in the circuit.
Steps: Simply Run The Wrapper
Side Notes: You may need to change the name of files and Top module in Wrapper and in Python File
Requirements: Download all the files at one location(directory) including .exe, .v and various other files.
We have used Yosys: http://www.clifford.at/yosys/ and SCOAP tool: https://sourceforge.net/projects/testabilitymeasurementtool/ as primary tools for the project
Video: https://youtu.be/RB_rpYwMU44