🔱 BCD to Binary Conversion 🔱

A BCD-to-binary conversion converts a BCD number to the equivalent binary representation. Assume that the input is an 8-bit signal in BCD format (i.e., two BCD digits) and the output is a 7-bit signal in binary representation.

code

''' `timescale 1ns / 1ps

module pes_bcdbin( input clk,rst_n, input start, input[3:0] dig1,dig0, output reg[6:0] bin, //2-digit number takes at most 7 bits output reg ready,done_tick ); //FSM state declarations localparam[1:0] idle=2'd0, op=2'd1, done=2'd2; reg[1:0] state_reg,state_nxt; reg[6:0] bin_nxt; reg[3:0] dig1_reg,dig1_nxt; reg[3:0] dig0_reg,dig0_nxt; reg[2:0] n_reg,n_nxt; //stores the width of the resulting binary

 //FSM register operation
 always @(posedge clk,negedge rst_n) begin
	if(!rst_n) begin
		state_reg<=idle;
		bin<=0;
		dig1_reg<=0;
		dig0_reg<=0;
		n_reg<=0;
	end
	else begin
		state_reg<=state_nxt;
		bin<=bin_nxt;
		dig1_reg<=dig1_nxt;
		dig0_reg<=dig0_nxt;
		n_reg<=n_nxt;
	end
 end
 //FSM next-state logic
 always @* begin
	state_nxt=state_reg;
	bin_nxt=bin;
	dig1_nxt=dig1_reg;
	dig0_nxt=dig0_reg;
	n_nxt=n_reg;
	ready=0;
	done_tick=0;
	case(state_reg)
			idle: begin
						ready=1;
						if(start) begin
							bin_nxt=0;
							dig1_nxt=dig1;
							dig0_nxt=dig0;
							n_nxt=7; //binary has 7 bits of output thus 7 "shifts" are needed
							state_nxt=op;
						end
					end
			  op: begin //special shift-operation for converting bcd to bin.Check the book for more info
						if( {dig1_reg[0],dig0_reg[3:1]} >= 8 ) ///special shift-operation for converting bcd to bin.Check the book for more info
							dig0_nxt= {dig1_reg[0],dig0_reg[3:1]} - 3;
						else dig0_nxt= {dig1_reg[0],dig0_reg[3:1]};
						dig1_nxt=dig1_reg>>1;
						bin_nxt={dig0_reg[0],bin[6:1]};
						n_nxt=n_reg-1;
						if(n_nxt==0) state_nxt=done;
					end
			done: begin
						done_tick=1;
						state_nxt=idle;
					end
		default: state_nxt=idle;
	endcase
 end

endmodule

'''

Simulation

iverilog pes_bcdbin.v pes_bcdbin_tb.v
./a.out
gtkwave pes_bcdbin_tb.vcd

Synthesis

read_liberty -lib ../pes_asic_class/sky130RTLDesignAndSynthesisWorkshop/lib/sky130_fd_sc_hd__tt_025C_1v80.lib 
read_verilog pes_bcdbin.v
synth -top pes_bcdbin
abc -liberty ../pes_asic_class/sky130RTLDesignAndSynthesisWorkshop/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
show

GLS

Stage 2 (RTL2GDSII - OPENLANE) - Table of contents

Design Stages

1. Synthesis

   1. yosys - Yosys performs RTL synthesis, converting high-level RTL descriptions into gate-level netlists.
   2. abc - ABC is used for further optimization and technology mapping to enhance the gate-level design.
   3. OpenSTA - OpenSTA conducts static timing analysis to verify if the synthesized design meets timing constraints in the OpenLane flow.

2. Floorplan & PND

   1. init_fp (Initial Floorplan) - Floorplanning involves determining the initial placement and arrangement of various functional blocks or cells within the chip's
      layout area.
   2. ioplacer - ioplacer is a tool used in the physical design process to place Input/Output (I/O) pads or pins on the chip's boundary.
   3. pdn - The PDN is responsible for distributing power (supply voltage) and ground (reference voltage) throughout the chip, ensuring that all components receive the necessary power supply and maintain stable electrical operation.
   4. tapcell - A "tapcell" is a special type of cell used in digital integrated circuit design, particularly in standard cell libraries.It is typically used to create tap connections for the bulk terminals in digital CMOS (Complementary Metal-Oxide-Semiconductor) designs.

3. Placement

   1. Replace - RePlace is a tool used in the OpenLane flow for cell placement optimization.It focuses on optimizing the placement of standard cells within the chip's
      layout to achieve better area utilization, timing, and power efficiency.
   2. Resizer - Resizer is a tool employed during the physical design process to perform cell resizing and optimization.
   3. OpenDP (Open Detailed Placement) - OpenDP, or Open Detailed Placement, is a detailed placement tool used in OpenLane.It is responsible for the fine-grained placement of cells, ensuring that they are precisely positioned within rows and tracks while adhering to design constraints and achieving optimal utilization of the chip's layout area.
   4. OpenPhysyn (Open Physical Synthesis) - OpenPhysyn is a tool within OpenLane that performs physical synthesis tasks.It optimizes the logical and physical aspects of the design simultaneously, improving the placement, power, area, and timing by considering both logic and physical information during the optimization process.

4. CTS

   1. TritonCTS - TritonCTS generates a clock distribution network.

5. Routing

   1. FastRoute - FastRoute is a global routing tool used in the physical design stage of ASIC chip design.
   2. TritonRoute - TritonRoute is a detailed or global routing tool used in the later stages of ASIC chip design, following placement and initial global routing.

6. GDSII Generation

   1. Magic - Magic is primarily a layout tool used for creating and editing IC layouts, and it is often used for digital CMOS design.
   2. KLayout - KLayout is primarily used for viewing, editing, and analyzing IC layouts but is not a layout creation tool like Magic.

7. Checks

   1. CVC - CVC is a tool primarily used for verification and debugging of digital designs.
   2. Netgen - Netgen is an open-source digital netlist comparison and LVS (Layout vs. Schematic) tool.

Open terminal and type the following commands.

cd OpenLane/ 
make mount 
./flow.tcl -interactive
package require openlane 0.9
prep -design openlane/pes_bcdbin -tag run-1

Synthesis

• Command to exectue

run_synthesis

Floorplan

• Command to exectue

run_floorplan

Note we need to use libs.tech file so we need to gitclone this https://github.com/hwiiiii/sky130A into pdks folder

git clone https://github.com/hwiiiii/sky130A

magic -T /home/mohankrishna/sky130A/sky130A/1lbs.tech/magic/sky130A. tech lef read ../../tmp/merged.nom.lef def read pes_bcdbin.def

Placement

• Command to exectue

run_placement

magic -T /home/mohankrishna/sky130A/sky130A/1lbs.tech/magic/sky130A. tech lef read ../../tmp/merged.nom.lef def read pes_bcdbin.def

CTS

• Command to exectue

run_cts

Routing

• Command to exectue

run_routing

magic -T /home/mohankrishna/sky130A/sky130A/1lbs.tech/magic/sky130A. tech lef read ../../tmp/merged.nom.lef def read pes_bcdbin.def

These reports generated are given below , after executing run_routing command

Statistics

• Area = 1230 um2
• Internal Power = 2.81e-04 W
• Switching Power = 1.81e-04 W
• Leakage Power = 6.73e-10 W
• Total Power = 4.61e-04 W