False DRT-0126 error

[msingh9]

I am getting this error during pin_access command. Unfortunately, I can't share the tech file to reproduction. Tech file is correct and this via is defined between two layers. Tech file is used in production chips. My question is how layer numbers are assigned? Is it something to do with order in which layers are defined in tech file?

pin_access -bottom_routing_layer $min_routing_layer
-top_routing_layer $max_routing_layer

[ERROR DRT-0126] Non-consecutive layers for via VV_XX_450_450_450_450_VV.

[maliberty]

The layer order is defined by their appearance in the tech lef. The expectation for a via is that the cut layer and the two adjacent routing layers are the only layers used in the via.