Skip to content
This repository has been archived by the owner on Jun 2, 2024. It is now read-only.

Actions: TinyTapeout/tt07-verilog-template

Actions

test

Actions

Loading...
Loading

Show workflow options

Create status badge

Loading
test.yaml
14 workflow runs
14 workflow runs

Filter by Event

Filter by Status

Filter by Branch

Filter by Actor

test: change default testbench license to Apache-2.0 test #14: Commit b906f3d pushed by urish
May 30, 2024 14:14 50s main
main
May 30, 2024 14:14 50s
suppress warning for unused inputs test #13: Commit 2c112d6 pushed by urish
May 27, 2024 12:33 36s main
main
May 27, 2024 12:33 36s
docs: twitter account link test #12: Commit 7a4440c pushed by urish
May 12, 2024 20:01 33s main
main
May 12, 2024 20:01 33s
ci(fpga): experimental FPGA bitstream action test #11: Commit 67f5971 pushed by urish
May 2, 2024 08:41 36s main
main
May 2, 2024 08:41 36s
ci(fpga): experimental FPGA bitstream action test #10: Commit 33f31df pushed by urish
May 2, 2024 08:41 49s main
main
May 2, 2024 08:41 49s
Update README.md test #9: Commit 6229636 pushed by mattvenn
April 28, 2024 18:25 41s main
main
April 28, 2024 18:25 41s
docs: explain the "ena" pin better test #8: Commit 4bc03dd pushed by urish
April 22, 2024 06:47 40s main
main
April 22, 2024 06:47 40s
docs: link to explain about custom clock config test #7: Commit da3fd6a pushed by urish
April 20, 2024 19:43 36s main
main
April 20, 2024 19:43 36s
fix: disable "MAGIC_DEF_LABELS" in config.tcl test #6: Commit 3bb2b5b pushed by urish
April 20, 2024 19:39 35s main
main
April 20, 2024 19:39 35s
Update README.md test #5: Commit 53c0d23 pushed by mattvenn
April 19, 2024 18:05 36s main
main
April 19, 2024 18:05 36s
TT07 Verilog Project Template test #4: Commit 3d8eb83 pushed by urish
April 19, 2024 17:56 33s main
main
April 19, 2024 17:56 33s
TT07 Verilog Project Template test #3: Commit 08d98e2 pushed by urish
April 19, 2024 17:48 34s main
main
April 19, 2024 17:48 34s
TT07 Verilog Project Template test #2: Commit 1528e05 pushed by urish
April 19, 2024 17:47 35s main
main
April 19, 2024 17:47 35s
TT07 Verilog Project Template test #1: Commit 46172fb pushed by urish
April 19, 2024 17:45 38s main
main
April 19, 2024 17:45 38s