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Designed an O(n2*d) algorithm to find the most optimum implementations in a complex circuit which would otherwise have been exponential O(an). Finally, designed a hierarchical Logic Analyzer to predict signal propagation delays to validate the results. Tested various implementations for area-delay optimization.

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Uniquedex100/Logic_Gate_Optimizer_COL215

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Designed an O(n2*d) algorithm to find the most optimum implementations in a complex circuit which would otherwise have been exponential O(an). Finally, designed a hierarchical Logic Analyzer to predict signal propagation delays to validate the results. Tested various implementations for area-delay optimization.

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