0.9.6

SimEng 0.9.6 is the eighth release of the Simulation Engine. In this release, SimEng is considered to be a beta software therefore there are expected to be bugs and missing features. If you find a bug, such as a missing instruction or missing system call, please submit a PR, or report an issue and we’ll address it as soon as we can.

Please see RELEASE-NOTES.txt for more information about this beta release. Additionally, the documentation for this project can be found at https://uob-hpc.github.io/SimEng/index.html.

What's Changed

• Update AArch64 Contiguous NEON/SVE Loads by @FinnWilkinson in #330
• Update AArch64 NEON/SVE Stores by @FinnWilkinson in #332
• Added link for modsim23 poster by @jj16791 in #334
• New aarch64 insn support by @jj16791 in #335
• Various memory centric bug fixes by @jj16791 in #336
• Model accuracy improvements by @jj16791 in #337
• SST compile fix on MacOS by @FinnWilkinson in #338
• SME SVCR logic fix by @FinnWilkinson in #339
• RISC-V Single and Double Precision Floating Point extension by @dANW34V3R in #303
• Global siminfo by @jj16791 in #343
• Register bug fixes by @jj16791 in #363
• Correct CSRRW State Change by @dANW34V3R in #364
• Memory interface type check by @jj16791 in #373
• Unit Test Suite Update by @FinnWilkinson in #352
• Added .cache to gitignore by @rahahahat in #353
• Added fix for returning a consistent nan value from a divide by zero by @jj16791 in #381
• st1w dirtied memory fix by @jj16791 in #383
• Config file bug cleanup by @JosephMoore25 in #370
• Fix broken tests caused by config-bug-fixes PR by @JosephMoore25 in #388
• Perceptron predictor by @ABenC377 in #374
• Name changes by @dANW34V3R in #377
• Architecture Class cleanup by @FinnWilkinson in #385
• Core class cleanup by @FinnWilkinson in #387
• Instruction Class Clean-Up by @FinnWilkinson in #389
• System call and exception regression tests by @jj16791 in #379
• RISC-V Compressed Instructions by @dANW34V3R in #368
• Added conditional existence checks before early config option querying by @jj16791 in #392
• AArch64 bitfieldManipulate bounds checking by @jj16791 in #395
• 0.9.6 update by @jj16791 in #396

New Contributors

• @JosephMoore25 made their first contribution in #370
• @ABenC377 made their first contribution in #374

Full Changelog: 0.9.5...0.9.6

0.9.5

SimEng 0.9.5 is the seventh release of the Simulation Engine. In this release, SimEng is considered to be a beta software therefore there are expected to be bugs and missing features. If you find a bug, such as a missing instruction or missing system call, please submit a PR, or report an issue and we’ll address it as soon as we can.

Please see RELEASE-NOTES.txt for more information about this beta release. Additionally, the documentation for this project can be found at https://uob-hpc.github.io/SimEng/index.html.

What's Changed

• Correcting instantiation of dispatches vector by @jj16791 in #257
• Initial SME Support by @FinnWilkinson in #248
• Initial SST SimEng integration by @rahahahat in #271
• RISC-V Support by @dANW34V3R in #234
• Fix memory leak in Linux::getdents64 by @tom91136 in #267
• Don't const qualify things we'll be moving later. by @tom91136 in #265
• Don't use type punning for RegressionTest::getMemoryValue by @tom91136 in #264
• Fix NUM_GROUPS warning by @dANW34V3R in #278
• AArch64 Instruction support & minor bug fixes by @FinnWilkinson in #273
• Correctly Fill Auxiliary Vector by @dANW34V3R in #300
• Documentation for SST by @rahahahat in #305
• RISC-V Docs by @dANW34V3R in #319
• Various updates to SimEng documentation by @jj16791 in #318
• Fix Incorrect Loop Buffer Behaviour by @dANW34V3R in #306
• In-order Early Halting Fix by @dANW34V3R in #294
• Revert commitMicroOps Function by @dANW34V3R in #321

Full Changelog: 0.9.4...0.9.5

SimEng 0.9.4

SimEng 0.9.4 is the sixth release of the Simulation Engine. In this release, SimEng is considered to be a beta software therefore there are expected to be bugs and missing features. If you find a bug, such as a missing instruction or missing system call, please submit a PR, or report an issue and we’ll address it as soon as we can.

Please see RELEASE-NOTES.txt for more information about this beta release. Additionally, the documentation for this project can be found at https://uob-hpc.github.io/SimEng/index.html.

What's Changed

• Documentation update for 0.9.4 by @jj16791 in #254
• Dispatch rate config option by @jj16791 in #251
• Output prefix by @jj16791 in #249
• New core creation by @jj16791 in #247
• Process Image memory optimisation by @rahahahat in #243
• Capstone update to support Armv9.2 by @FinnWilkinson in #239
• Minor feature fixes by @FinnWilkinson in #240
• Initial M1 Firestorm core model by @tomhepworth in #245
• Additional aarch64 and syscall support by @tomhepworth in #233
• Added comments explaining ELF file structure in Elf.cc file by @rahahahat in #242
• Prevent ExceptionHandler processing if there are active memory requests by @jj16791 in #235
• Updated jenkins armclang build script to use new armclang22 compiler by @jj16791 in #246
• New generic branch prediction by @jj16791 in #226
• Removed prefix from standard types such as due to build errors on some Linux machines by @FinnWilkinson
• Fix for sve FNEG (predicated) instruction by @FinnWilkinson in #230
• Updated some config options to be read as uint16_t not uint8_t to allow for a wider param space by @jj16791 in #229
• Missing sys reg handling by @jj16791 in #228
• Implemented functionality to update the Processor Cycle Counter system register (PMCCNTR_EL0 for Aarch64). by @FinnWilkinson
• Updated the Virtual Counter Timer logic to iterate at the Timer-Frequency, rather than update the VCT register to total cycles completed. by @FinnWilkinson

Full Changelog: 0.9.3...0.9.4

SimEng 0.9.3

SimEng 0.9.3 is the fifth release of the Simulation Engine. In this release, SimEng is considered to be a beta software therefore there are expected to be bugs and missing features. If you find a bug, such as a missing instruction or missing system call, please submit a PR, or report an issue and we’ll address it as soon as we can.

Please see RELEASE-NOTES.txt for more information about this beta release. Additionally, the documentation for this project can be found at https://uob-hpc.github.io/SimEng/index.html.

What's Changed

• Documentation update for 0.9.3 by @jj16791 in #225
• Improved LoadStoreQueue scheduler and load-store reordering conflict detection by @jj16791
• Simple support for some armv8.4-a load and store macro-op splitting by @jj16791 in #220
• Support for FFTW code (http://fftw.org/) by @FinnWilkinson in #219

Full Changelog: 0.9.2...0.9.3

SimEng 0.9.2

SimEng 0.9.2 is the fourth release of the Simulation Engine. In this release, SimEng is considered to be a beta software therefore there are expected to be bugs and missing features. If you find a bug, such as a missing instruction or missing system call, please submit a PR, or report an issue and we’ll address it as soon as we can.

Please see RELEASE-NOTES.txt for more information about this beta release. Additionally, the documentation for this project can be found at https://uob-hpc.github.io/SimEng/index.html.

What's Changed

• Minor bug fixes by @jj16791 in #210
• Recofiguration of the instruction execution logic using helper functions by @FinnWilkinson in #212
• Documentation update for 0.9.2 release by @FinnWilkinson in #215

Full Changelog: 0.9.1...0.9.2

SimEng 0.9.1

SimEng 0.9.1 is the third release of the Simulation Engine. In this release, SimEng is considered to be a beta software therefore there are expected to be bugs and missing features. If you find a bug, such as a missing instruction or missing system call, please submit a PR, or report an issue and we’ll address it as soon as we can.

Please see RELEASE-NOTES.txt for more information about this beta release. Additionally, the documentation for this project can be found at https://uob-hpc.github.io/SimEng/index.html.

What's Changed

• Further AArch64 coverage targeting the CloverLeaf benchmark by @FinnWilkinson in #199
• Further AArch64 Support & Syscall OS Nuance Fixes by @FinnWilkinson in #201
• Variable SVE vector length by @jj16791 in #204
• Improved Special Files Support by @FinnWilkinson in #206
• Documentation update for 0.9.1 release by @jj16791 in #207

Full Changelog: 0.9.0...0.9.1

SimEng 0.9.0

SimEng 0.9.0 is the second release of the Simulation Engine. In this release, SimEng is considered to be a beta software therefore there are expected to be bugs and missing features. If you find a bug, such as a missing instruction or missing system call, please submit a PR, or report an issue and we’ll address it as soon as we can.

Please see RELEASE-NOTES.txt for more information about this beta release. Additionally, the documentation for this project can be found at https://uob-hpc.github.io/SimEng/index.html.

What's Changed

• Optimizations by @mutalibmohammed in #191
• Bug fixes by @mutalibmohammed in #192
• CloverLeaf and TeaLeaf Benchmark Support by @FinnWilkinson in #195
• Minifmm support by @viper12590 in #197
• Documentation update for 0.9.0 release by @jj16791 in #198

Full Changelog: 0.8.0...0.9.0

SimEng 0.8.0

SimEng 0.8.0 is the first open source release of the Simulation Engine. In this release, SimEng is considered to be an alpha software therefore there are expected to be bugs and missing features. If you find a bug, such as a missing instruction or missing system call, please submit a PR, or report an issue and we’ll address it as soon as we can.

Please see RELEASE-NOTES.txt for more information about this alpha release. Additionally, the documentation for this project can be found at https://uob-hpc.github.io/SimEng/index.html.