GitHub - Vanaub22/VHDL: These are VHDL codes that I wrote as a part of our Computer Architecture Course in the 4th Semester.

Computer Architecture Lab (PCC-CS492)

VHDL stands for VHSIC Hardware Description Language.
VHSIC stands for Very High Speed Integrated Circuit.

These are basically all my VHDL Codes that I developed during my 4th Semester of Engineering as a part of my Computer Architecture Laboratory Coursework on the Xilinx ISE Platform.

Name		Name	Last commit message	Last commit date
Latest commit History 19 Commits
README.md		README.md
alu_rtl.vhd		alu_rtl.vhd
alu_test.vhd		alu_test.vhd
and_rtl.vhd		and_rtl.vhd
and_test.vhd		and_test.vhd
comparator_rtl.vhd		comparator_rtl.vhd
comparator_test.vhd		comparator_test.vhd
composite_rtl.vhd		composite_rtl.vhd
composite_test.vhd		composite_test.vhd
counter_rtl.vhd		counter_rtl.vhd
counter_test.vhd		counter_test.vhd
d_ff_rtl.vhd		d_ff_rtl.vhd
d_ff_test.vhd		d_ff_test.vhd
demultiplexer_rtl.vhd		demultiplexer_rtl.vhd
demultiplexer_test.vhd		demultiplexer_test.vhd
four_bit_sub_rtl.vhd		four_bit_sub_rtl.vhd
fourbit_adder_rtl.vhd		fourbit_adder_rtl.vhd
fourbit_adder_test.vhd		fourbit_adder_test.vhd
fourbit_sub_test.vhd		fourbit_sub_test.vhd
full_adder_rtl.vhd		full_adder_rtl.vhd
full_adder_test.vhd		full_adder_test.vhd
full_adder_using_ha.vhd		full_adder_using_ha.vhd
full_adder_using_ha_test.vhd		full_adder_using_ha_test.vhd
half_adder_rtl.vhd		half_adder_rtl.vhd
half_adder_test.vhd		half_adder_test.vhd
jk_ff_rtl.vhd		jk_ff_rtl.vhd
jk_ff_test.vhd		jk_ff_test.vhd
multiplexer_rtl.vhd		multiplexer_rtl.vhd
multiplexer_test.vhd		multiplexer_test.vhd
nand_rtl.vhd		nand_rtl.vhd
nand_test.vhd		nand_test.vhd
or_rtl.vhd		or_rtl.vhd
or_test.vhd		or_test.vhd
piso_rtl.vhd		piso_rtl.vhd
piso_test.vhd		piso_test.vhd
sipo_rtl.vhd		sipo_rtl.vhd
sipo_test.vhd		sipo_test.vhd
sr_ff_rtl.vhd		sr_ff_rtl.vhd
sr_ff_test.vhd		sr_ff_test.vhd

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