README.md

MultiBank Memory Design in SystemVerilog

Overview

The project explores the concept of multibank memory systems as a particular solution of multiport memory problem. The aims of the project is to find the optimal number of banks to minimize conflicts and maximize throughput, as described in the article "Multibank memory bandwidth analysis in on-chip system." (link)

• Scalebility: you can adjast the number of ports and memory banks;
• Ready/Valid interface: module interaction use ready/valid interface.
  Currently there is a problem with implementing an efficient ready/valid interface for the read port. It means that the read port has an additional 1 clock delay;
• Ports arbitration: When multiple ports are handled simultaneously, the processing order is arbitrary, but the number of stall clock cycles cannot be greater than the number of ports;
• Read constant memory delay: After the read transaction is validated, the response comes after several clock cycles. The number of clock cycles is fixed and equal to the delay of memory block reading. The data is accompanied by an ready signal;
• Write constant memory delay: After the write transaction is validated, the data will be written to memory within a few clock cycles. The number of clock cycles is fixed and equal to the delay of memory block writing.

Contents

• src/design/: Source code for the multibank memory module.
• src/testbench/: Files for verification and throughput examination.
• docs/: Documentation and additional resources.

Project Details

• Course: Digital Circuit Design
• University: Innopolis University
• Authors: Artem Voronov and Roman Voronov

Getting Started

Prerequisites

• Modelsim or QuestaSim

Installation

1. Clone the repository:

   git clone https://github.com/Vor-Art/DCD_MultiBankMemory.git
   cd DCD_MultiBankMemory/src

2. Launch test and display results:

   modelsim -do ./run.do
   cat test_results.txt

Note: you can specify the test by setting the parameter test_id in run.do:
test_id=0: Direct test - static set of simple tests to check correctness;
test_id=1: Random test - each port access to random addresses each time;
test_id=2: todo...

Documentation

Related Article

Our paper is published on 2021 MES Conference. The article "Multibank memory bandwidth analysis in on-chip system" is available in the doc/article/ directory. This publication provides in-depth analysis and insights into the design and performance of the multibank memory module.

For citation use:

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A. V. Voronov, R. V. Voronov, and R. F. Iliasov, “Multibank memory bandwidth analysis in on-chip system,” Problems of advanced micro- and nanoelectronic systems development. FSFIS Institute for Design Problems in Microelectronics RAS, pp. 99–105, 2021. doi: 10.31114/2078-7707-2021-4-99-105

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Presentation

The slides of the project presentation are available in the doc/presentation/ directory. These slides provide explained details and key findings.

Usefull links

• Understanding Multiport-Memories: Considers various implementation of multiport memory (Flip-Flop, Live Value Table, XOR-Based, etc...)
• Collection of Multi-Ported Memories: Collects various articles related to multiport memory for FPGAs (and ASICs too)
• Arbiters: Design Ideas and Coding Styles: Describes the implementation of various arbitration methods.

Acknowledgments

Thanks to Yuri Panchul for advising us on the concept of multiport memory. We are thankful to Dmitry Smekhov for preparing the testbench for memory design and Innopolis University for inspiration in writing an article on this topic.