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bump llvm to llvmorg-19.1.0
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@yamt
yamt committed Sep 18, 2024
1 parent 85972e0 commit 254a9e7
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion src/llvm-project
Submodule llvm-project updated 90 files
+13 −2 .github/workflows/release-binaries.yml
+1 −1 .github/workflows/release-sources.yml
+3 −0 clang/docs/ReleaseNotes.rst
+4 −0 clang/lib/Basic/Targets/X86.cpp
+61 −85 clang/lib/CodeGen/CGCall.cpp
+14 −9 clang/lib/CodeGen/CGExprAgg.cpp
+1 −1 clang/lib/CodeGen/CGStmt.cpp
+4 −3 clang/lib/CodeGen/CodeGenFunction.h
+4 −2 clang/lib/Format/UnwrappedLineParser.cpp
+17 −4 clang/lib/Sema/SemaExpr.cpp
+2 −1 clang/lib/Sema/SemaExprCXX.cpp
+0 −1 clang/lib/Sema/SemaLambda.cpp
+1 −1 clang/lib/Sema/SemaLookup.cpp
+1 −4 clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
+12 −0 clang/test/Analysis/embed.c
+27 −16 clang/test/CodeGen/arm-mve-intrinsics/vld24.c
+5 −5 clang/test/CodeGen/arm-vfp16-arguments2.cpp
+1 −0 clang/test/CodeGen/target-builtin-noerror.c
+4 −7 clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
+58 −67 clang/test/CodeGenCUDA/builtins-amdgcn.cu
+57 −66 clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
+3 −3 clang/test/CodeGenCXX/address-space-cast-coerce.cpp
+23 −1 clang/test/CodeGenCXX/cxx2a-consteval.cpp
+20 −0 clang/test/CodeGenCXX/trivial_abi.cpp
+4 −4 clang/test/CodeGenHIP/dpp-const-fold.hip
+4 −4 clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
+9 −2 clang/test/CodeGenOpenCL/addr-space-struct-arg.cl
+27 −15 clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl
+4 −0 clang/test/Driver/x86-march.c
+1 −0 clang/test/Frontend/x86-target-cpu.c
+4 −4 clang/test/Misc/target-invalid-cpu-note.c
+142 −0 clang/test/Preprocessor/predefined-arch-macros.c
+9 −0 clang/test/SemaCXX/cxx23-assume.cpp
+4 −2 clang/test/SemaCXX/cxx2c-placeholder-vars.cpp
+60 −0 clang/test/SemaCXX/source_location.cpp
+18 −0 clang/test/SemaCXX/type-traits.cpp
+15 −0 clang/unittests/Format/TokenAnnotatorTest.cpp
+1 −1 cmake/Modules/LLVMVersion.cmake
+20 −0 compiler-rt/lib/builtins/cpu_model/x86.c
+1 −1 compiler-rt/lib/builtins/divtc3.c
+1 −1 compiler-rt/lib/builtins/multc3.c
+1 −1 libcxx/include/chrono
+3 −5 lld/ELF/Arch/Hexagon.cpp
+5 −0 lld/test/ELF/hexagon-eflag.s
+4 −0 llvm/docs/ReleaseNotes.rst
+3 −0 llvm/include/llvm/TargetParser/X86TargetParser.def
+1 −0 llvm/include/llvm/TargetParser/X86TargetParser.h
+3 −0 llvm/lib/CodeGen/ModuloSchedule.cpp
+4 −0 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+10 −2 llvm/lib/IR/BasicBlock.cpp
+0 −33 llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+0 −4 llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+18 −12 llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+5 −4 llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+1 −1 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+15 −0 llvm/lib/Target/X86/X86.td
+1 −0 llvm/lib/Target/X86/X86PfmCounters.td
+19 −0 llvm/lib/TargetParser/Host.cpp
+5 −0 llvm/lib/TargetParser/X86TargetParser.cpp
+7 −1 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+66 −38 llvm/test/CodeGen/AArch64/sme-vg-to-stack.ll
+944 −544 llvm/test/CodeGen/AArch64/sme2-intrinsics-ld1.ll
+944 −544 llvm/test/CodeGen/AArch64/sme2-intrinsics-ldnt1.ll
+36 −1 llvm/test/CodeGen/AArch64/spillfill-sve.mir
+82 −58 llvm/test/CodeGen/AArch64/sve-callee-save-restore-pairs.ll
+98 −0 llvm/test/CodeGen/AMDGPU/mul_int24.ll
+217 −0 llvm/test/CodeGen/Hexagon/swp-ws-live-intervals.mir
+22 −0 llvm/test/CodeGen/PowerPC/f128-bitcast.ll
+98 −6 llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir
+18 −0 llvm/test/CodeGen/WinEH/wineh-empty-seh-scope.ll
+1 −0 llvm/test/CodeGen/X86/bypass-slow-division-64.ll
+1 −0 llvm/test/CodeGen/X86/cmp16.ll
+1 −0 llvm/test/CodeGen/X86/cpus-amd.ll
+1 −0 llvm/test/CodeGen/X86/rdpru.ll
+1 −0 llvm/test/CodeGen/X86/shuffle-as-shifts.ll
+1 −0 llvm/test/CodeGen/X86/slow-unaligned-mem.ll
+1 −0 llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
+1 −0 llvm/test/CodeGen/X86/tuning-shuffle-permilpd-avx512.ll
+1 −0 llvm/test/CodeGen/X86/tuning-shuffle-permilps-avx512.ll
+1 −0 llvm/test/CodeGen/X86/tuning-shuffle-unpckpd-avx512.ll
+1 −0 llvm/test/CodeGen/X86/tuning-shuffle-unpckps-avx512.ll
+1 −0 llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll
+1 −0 llvm/test/CodeGen/X86/vpdpwssd.ll
+1 −0 llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
+2 −0 llvm/test/MC/X86/x86_long_nop.s
+1 −0 llvm/test/Transforms/LoopUnroll/X86/call-remark.ll
+31 −0 llvm/test/Transforms/SLPVectorizer/X86/minbw-user-non-sizable.ll
+49 −0 llvm/test/Transforms/SLPVectorizer/X86/operand-is-reduced-val.ll
+1 −0 llvm/test/Transforms/SLPVectorizer/X86/pr63668.ll
+52 −0 llvm/unittests/IR/BasicBlockDbgInfoTest.cpp

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