diff --git a/README.md b/README.md index bd023d51..e4dd9fe7 100644 --- a/README.md +++ b/README.md @@ -1,30 +1,103 @@ -## 简介 +English | [简体中文](./README_CN.md) -SHL(曾用名CSI-NN2) 是 T-HEAD 提供的一组针对玄铁 CPU 平台的神经网络库 API。抽象了各种常用的网络层的接口，并且提供一系列已优化的二进制库。 +SHL(Structure of Heterogeneous Library, Chinese name: ShiHulan) is a high-performance Heterogeneous computing library provided by T-HEAD. +The interface of SHL uses T-HEAD neural network library API for XuanTie CPU platform: CSI-NN2, and provides a series of optimized binary libraries. -SHL 的特性： +Features for SHL: -- C 代码版本的参考实现。 -- 提供玄铁系列 CPU 的汇编优化实现。 -- 支持对称量化和非对称量化。 -- 支持8位定点，16位定点和16位浮点等数据类型。 -- 兼容 NCHW 和 NHWC 格式。 -- 搭配 [HHB](https://www.yuque.com/za4k4z/oxlbxl) 实现代码自动调用。 -- 覆盖 CPU，NPU 等不同体系结构。 -- 附加异构参考实现。 +- Reference implementation of c code version +- Assembly optimization implementation for XuanTie CPU +- Supports symmetric quantization and asymmetric quantization +- Support 8bit, 16bit, and f16 data types +- compaatible with NCHW and NHWC formates +- Use [HHB](https://www.yuque.com/za4k4z/kvkcoh) to automatically call API +- Covers different architectures, such as CPU and NPU +- Reference heterogeneous schedule implementation -SHL 提供了完成的接口声明和接口的参考实现，各个设备提供商可以依此针对性的完成各个接口的优化工作。 +In principle, SHL only provides the reference implementation of XuanTie CPU platform, and the optimization of each NPU target platform is completed by the vendor of the specific platform. -## 文档说明 +# Use SHL -- [中文文档](https://www.yuque.com/za4k4z/isgz8o) +- [SHL API](https://www.yuque.com/za4k4z/kkzsw9) +- [SHL deployment tools](https://www.yuque.com/za4k4z/kvkcoh) -## 致谢 +# Installation + +## Official Python packages + +SHL released packages are published in PyPi, can install with hhb. + +``` +pip3 install hhb +``` + +binary libary is at /usr/local/lib/python3.6/dist-packages/tvm/install_nn2/ + +## Build SHL from Source + +Here is one example to build C906 library. + +We need to install T-HEAD RISC-V GCC 2.6, which can get from T-HEAD OCC, download, decompress, and set path environment. + +``` +wget https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1663142514282/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.6.1-20220906.tar.gz +tar xf Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.6.1-20220906.tar.gz +export PATH=${PWD}/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.6.1/bin:$PATH +``` + +Download source code + +``` +git clone https://github.com/T-head-Semi/csi-nn2.git +``` + +compile c906 + +``` +cd csi-nn2 +make nn2_c906 +``` + +install c906 + +``` +make install_nn2 +``` + +# Quick Start Example + +Here is one example for XuanTie C906 to run mobilenetv1. It shows how to call SHL API to inference the whole model. + +compile command: + +``` +cd example +make c906_m1_f16 +``` + +c906_mobilenetv1_f16.elf will be generated after completion. +After copying it to the development board with C906 CPU [such as D1], execute: + +``` +./c906_mobilenetv1_f16.elf +``` + +NOTE: Original mobilenetv1's every conv2d has one BN(batch norm), but the example assumes BN had been fused into conv2d。About how to use deployment tools to fuse BN, and emit right weight float16 value, can reference [HHB](https://www.yuque.com/za4k4z/kvkcoh). + +# Resources + +- [T-HEAD Open Chip Community](https://xrvm.com/) +- [Use SHL to run MLPerf tiny](https://github.com/mlcommons/tiny_results_v0.7/tree/main/open/Alibaba) + +## Acknowledgement + +SHL refers to the following projects: -SHL 参考、借鉴了下列项目： - [Caffe](https://github.com/BVLC/caffe) - [Tensorflow](https://github.com/tensorflow/tensorflow) - [ncnn](https://github.com/Tencent/ncnn) - [MNN](https://github.com/alibaba/MNN) - [Tengine](https://github.com/OAID/Tengine) - [CMSIS_5](https://github.com/ARM-software/CMSIS_5) +- [ONNX](https://github.com/onnx/onnx) +- [XNNPACK](https://github.com/google/XNNPACK) diff --git a/README_CN.md b/README_CN.md new file mode 100644 index 00000000..1b9bbb90 --- /dev/null +++ b/README_CN.md @@ -0,0 +1,100 @@ + [English](./README.md) | 简体中文 + +SHL 是 T-HEAD 提供的一组针对玄铁 CPU 平台的神经网络库 API。抽象了各种常用的网络层的接口，并且提供一系列已优化的二进制库。 + +SHL 的特性： + +- C 代码版本的参考实现。 +- 提供玄铁系列 CPU 的汇编优化实现。 +- 支持对称量化和非对称量化。 +- 支持8位定点，16位定点和16位浮点等数据类型。 +- 兼容 NCHW 和 NHWC 格式。 +- 搭配 [HHB](https://www.yuque.com/za4k4z/oxlbxl) 实现代码自动调用。 +- 覆盖 CPU，NPU 等不同体系结构。 +- 附加异构参考实现。 + +SHL 提供了完成的接口声明和接口的参考实现，各个设备提供商可以依此针对性的完成各个接口的优化工作。 + +# 使用 SHL + +- [SHL 接口和设计文档](https://www.yuque.com/za4k4z/isgz8o) +- [SHL 配套部署工具](https://www.yuque.com/za4k4z/oxlbxl) + +# 安装 + +## 通过 PyPi 安装 + +SHL 的预编译库可以通过 PyPi 安装 hhb 时，一起安装。 + +``` +pip3 install hhb +``` + +二进制库的安装目录在 /usr/local/lib/python3.6/dist-packages/tvm/install_nn2/ + +## 通过源码重新编译 + +以 Ubuntu 上编译 c906 优化为例。 + +编译 C906 需要用到 T-HEAD RISC-V GCC， 从 OCC 下载 GCC 2.6 版本，解压并设置路径。 + +``` +wget https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1663142514282/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.6.1-20220906.tar.gz +tar xf Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.6.1-20220906.tar.gz +export PATH=${PWD}/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.6.1/bin:$PATH +``` + +下载源码 + +``` +git clone https://github.com/T-head-Semi/csi-nn2.git +``` + +编译 c906 + +``` +cd csi-nn2 +make nn2_c906 +``` + +安装 c906 + +``` +make install_nn2 +``` + +# 快速上手示例 + +以玄铁 CPU C906 执行 mobilenetv1 为例，可以参考 example 中的示例，示例中以较简易的方式描述了如何调用 SHL 的接口。 + +编译命令如下： + +``` +cd example +make c906_m1_f16 +``` + +完成后会生成 c906_mobilenetv1_f16.elf 文件。将其复制到带 C906 CPU 的开发板【比如 D1】后，执行： + +``` +./c906_mobilenetv1_f16.elf +``` + +NOTE: 原始 mobilenetv1 中每层 conv2d 后接一层 batch norm，示例中假设已经通过部署工具将其融合进 conv2d。关于如何使用部署工具融合 batch norm，以及生成对应的权重数值，可以参考 [HHB](https://www.yuque.com/za4k4z/oxlbxl) 的使用。 + +# 资源 + +- [T-HEAD 芯片开放社区](https://occ.t-head.cn/) +- [SHL 应用在 MLPerf tiny](https://github.com/mlcommons/tiny_results_v0.7/tree/main/open/Alibaba) + +# 致谢 + +SHL 参考、借鉴了下列项目： +- [Caffe](https://github.com/BVLC/caffe) +- [Tensorflow](https://github.com/tensorflow/tensorflow) +- [ncnn](https://github.com/Tencent/ncnn) +- [MNN](https://github.com/alibaba/MNN) +- [Tengine](https://github.com/OAID/Tengine) +- [CMSIS_5](https://github.com/ARM-software/CMSIS_5) +- [ONNX](https://github.com/onnx/onnx) +- [XNNPACK](https://github.com/google/XNNPACK) diff --git a/example/Makefile b/example/Makefile new file mode 100644 index 00000000..8df80e4e --- /dev/null +++ b/example/Makefile @@ -0,0 +1,9 @@ + +c906_m1_f16: + riscv64-unknown-linux-gnu-gcc c906_mobilenetv1_f16.c -o c906_mobilenetv1_f16.elf -I../include ../install_nn2/lib/libshl_c906.a -lm -static + +c906_c2d_f32: + riscv64-unknown-linux-gnu-gcc c906_conv2d_f32.c -o c906_conv2d_f32.elf -I../include ../install_nn2/lib/libshl_c906.a -lm -static + +clean: + rm -rf *.elf diff --git a/example/c906_conv2d_f32.c b/example/c906_conv2d_f32.c new file mode 100644 index 00000000..f45522f4 --- /dev/null +++ b/example/c906_conv2d_f32.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2016-2022 T-Head Semiconductor Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* SHL version 2.1.x */ + +#include + +int main(int argc, char **argv) +{ + struct csinn_session *sess = csinn_alloc_session(); + sess->base_run_mode = CSINN_RM_LAYER; + struct csinn_tensor *input = csinn_alloc_tensor(sess); + struct csinn_tensor *output = csinn_alloc_tensor(sess); + struct csinn_tensor *kernel = csinn_alloc_tensor(sess); + struct csinn_tensor *bias = csinn_alloc_tensor(sess); + struct csinn_conv2d_params *params = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + + input->dim[0] = 1; // batch + input->dim[1] = 512; // in_channel + input->dim[2] = 14; // height + input->dim[3] = 14; // width + kernel->dim[0] = 512; + kernel->dim[1] = 512; + kernel->dim[2] = 1; + kernel->dim[3] = 1; + bias->dim[0] = 512; + output->dim[0] = 1; // batch + output->dim[1] = 512; // out_channel + output->dim[2] = 14; // height + output->dim[3] = 14; // width + + params->stride_height = 1; + params->stride_width = 1; + params->pad_left = 0; + params->pad_right = 0; + params->pad_top = 0; + params->pad_down = 0; + params->dilation_width = 0; + params->dilation_height = 0; + params->base.layout = CSINN_LAYOUT_NCHW; + params->group = 1; + params->conv_extra.fuse_zp2bias = false; + + input->dim_count = 4; + input->layout = CSINN_LAYOUT_NCHW; + input->is_const = 0; + input->quant_channel = 1; + + kernel->dim_count = 4; + kernel->layout = CSINN_LAYOUT_OIHW; + kernel->is_const = 1; + kernel->quant_channel = 1; + + bias->dim_count = 1; + bias->layout = CSINN_LAYOUT_O; + bias->is_const = 1; + bias->quant_channel = 1; + + output->dim_count = 4; + output->layout = CSINN_LAYOUT_NCHW; + output->is_const = 0; + output->quant_channel = 1; + + input->dtype = CSINN_DTYPE_FLOAT32; + kernel->dtype = CSINN_DTYPE_FLOAT32; + bias->dtype = CSINN_DTYPE_FLOAT32; + output->dtype = CSINN_DTYPE_FLOAT32; + + params->base.api = CSINN_C906; + + /* alloc random input */ + input->data = malloc(14 * 14 * 512 * 4); + /* alloc random kernel */ + kernel->data = malloc(512 * 512 * 1 * 1 * 4); + /* alloc random bias */ + bias->data = malloc(512 * 4); + /* alloc random output */ + output->data = malloc(14 * 14 * 512 * 4); + + csinn_conv2d_init(input, output, kernel, bias, params); + + uint64_t start_time, end_time; + start_time = shl_get_timespec(); + csinn_conv2d(input, output, kernel, bias, params); + end_time = shl_get_timespec(); + printf("Run graph execution time: %.5fms, FPS=%.2f\n", + ((float)(end_time - start_time)) / 1000000, + 1000000000.0 / ((float)(end_time - start_time))); + + return 0; +} diff --git a/example/c906_mobilenetv1_f16.c b/example/c906_mobilenetv1_f16.c new file mode 100644 index 00000000..278c4f22 --- /dev/null +++ b/example/c906_mobilenetv1_f16.c @@ -0,0 +1,1983 @@ +/* + * Copyright (C) 2016-2022 T-Head Semiconductor Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* SHL version 2.1.x */ + +#include + +void *csinn_(char *params_base) +{ + struct csinn_session *sess = csinn_alloc_session(); + sess->base_run_mode = CSINN_RM_CPU_GRAPH; + sess->base_api = CSINN_C906; + sess->base_dtype = CSINN_DTYPE_FLOAT16; + csinn_session_init(sess); + csinn_set_input_number(1, sess); + csinn_set_output_number(1, sess); + + struct csinn_tensor *data = csinn_alloc_tensor(sess); + data->name = "data@@conv2d_conv1_0_fuse_multiply_1_fuse_add_conv1/bn_PART_0_2_0"; + data->dtype = CSINN_DTYPE_FLOAT16; + data->layout = CSINN_LAYOUT_NCHW; + data->dim[0] = 1; + data->dim[1] = 3; + data->dim[2] = 224; + data->dim[3] = 224; + data->dim_count = 4; + data->qinfo = (struct csinn_quant_info *)(params_base + 0); + data->quant_channel = 1; + struct csinn_tensor *output_0 = csinn_alloc_tensor(sess); + output_0->name = "output_0"; + output_0->dtype = CSINN_DTYPE_FLOAT16; + output_0->layout = CSINN_LAYOUT_NCHW; + output_0->dim[0] = 1; + output_0->dim[1] = 32; + output_0->dim[2] = 112; + output_0->dim[3] = 112; + output_0->dim_count = 4; + output_0->qinfo = (struct csinn_quant_info *)(params_base + 24); + output_0->quant_channel = 1; + struct csinn_tensor *kernel_0 = csinn_alloc_tensor(sess); + kernel_0->name = "kernel_0"; + kernel_0->data = params_base + 72; + kernel_0->is_const = 1; + kernel_0->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_0->dtype = CSINN_DTYPE_FLOAT16; + kernel_0->layout = CSINN_LAYOUT_OIHW; + kernel_0->dim[0] = 32; + kernel_0->dim[1] = 3; + kernel_0->dim[2] = 3; + kernel_0->dim[3] = 3; + kernel_0->dim_count = 4; + kernel_0->qinfo = (struct csinn_quant_info *)(params_base + 48); + kernel_0->quant_channel = 1; + struct csinn_tensor *bias_0 = csinn_alloc_tensor(sess); + bias_0->name = "bias_0"; + bias_0->data = params_base + 1856; + bias_0->is_const = 1; + bias_0->dtype = CSINN_DTYPE_FLOAT16; + bias_0->layout = CSINN_LAYOUT_O; + bias_0->dim[0] = 32; + bias_0->dim_count = 1; + bias_0->qinfo = (struct csinn_quant_info *)(params_base + 1832); + bias_0->quant_channel = 1; + struct csinn_conv2d_params *params_0 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_0->group = 1; + params_0->stride_height = 2; + params_0->stride_width = 2; + params_0->dilation_height = 1; + params_0->dilation_width = 1; + params_0->conv_extra.kernel_tm = NULL; + params_0->conv_extra.conv_mode = CSINN_DIRECT; + params_0->pad_top = 1; + params_0->pad_left = 1; + params_0->pad_down = 1; + params_0->pad_right = 1; + params_0->base.name = "conv2d_conv1_0_fuse_multiply_1_fuse_add_conv1/bn_PART_0_2"; + csinn_conv2d_init(data, output_0, kernel_0, bias_0, params_0); + struct csinn_tensor *output_1 = csinn_alloc_tensor(sess); + output_1->name = "output_1"; + output_1->dtype = CSINN_DTYPE_FLOAT16; + output_1->layout = CSINN_LAYOUT_NCHW; + output_1->dim[0] = 1; + output_1->dim[1] = 32; + output_1->dim[2] = 112; + output_1->dim[3] = 112; + output_1->dim_count = 4; + output_1->qinfo = (struct csinn_quant_info *)(params_base + 1920); + output_1->quant_channel = 1; + struct csinn_relu_params *params_1 = csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_1->base.name = "relu_relu1_3"; + csinn_relu_init(output_0, output_1, params_1); + struct csinn_tensor *output_2 = csinn_alloc_tensor(sess); + output_2->name = "output_2"; + output_2->dtype = CSINN_DTYPE_FLOAT16; + output_2->layout = CSINN_LAYOUT_NCHW; + output_2->dim[0] = 1; + output_2->dim[1] = 32; + output_2->dim[2] = 112; + output_2->dim[3] = 112; + output_2->dim_count = 4; + output_2->qinfo = (struct csinn_quant_info *)(params_base + 1944); + output_2->quant_channel = 1; + struct csinn_tensor *kernel_2 = csinn_alloc_tensor(sess); + kernel_2->name = "kernel_2"; + kernel_2->data = params_base + 1992; + kernel_2->is_const = 1; + kernel_2->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_2->dtype = CSINN_DTYPE_FLOAT16; + kernel_2->layout = CSINN_LAYOUT_O1HW; + kernel_2->dim[0] = 32; + kernel_2->dim[1] = 1; + kernel_2->dim[2] = 3; + kernel_2->dim[3] = 3; + kernel_2->dim_count = 4; + kernel_2->qinfo = (struct csinn_quant_info *)(params_base + 1968); + kernel_2->quant_channel = 1; + struct csinn_tensor *bias_2 = csinn_alloc_tensor(sess); + bias_2->name = "bias_2"; + bias_2->data = params_base + 2624; + bias_2->is_const = 1; + bias_2->dtype = CSINN_DTYPE_FLOAT16; + bias_2->layout = CSINN_LAYOUT_O; + bias_2->dim[0] = 32; + bias_2->dim_count = 1; + bias_2->qinfo = (struct csinn_quant_info *)(params_base + 2600); + bias_2->quant_channel = 1; + struct csinn_conv2d_params *params_2 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_2->group = 32; + params_2->stride_height = 1; + params_2->stride_width = 1; + params_2->dilation_height = 1; + params_2->dilation_width = 1; + params_2->conv_extra.kernel_tm = NULL; + params_2->conv_extra.conv_mode = CSINN_DIRECT; + params_2->pad_top = 1; + params_2->pad_left = 1; + params_2->pad_down = 1; + params_2->pad_right = 1; + params_2->base.name = "conv2d_conv2_1/dw_4_fuse_multiply_5_fuse_add_conv2_1/dw/bn_PART_0_6"; + csinn_conv2d_init(output_1, output_2, kernel_2, bias_2, params_2); + struct csinn_tensor *output_3 = csinn_alloc_tensor(sess); + output_3->name = "output_3"; + output_3->dtype = CSINN_DTYPE_FLOAT16; + output_3->layout = CSINN_LAYOUT_NCHW; + output_3->dim[0] = 1; + output_3->dim[1] = 32; + output_3->dim[2] = 112; + output_3->dim[3] = 112; + output_3->dim_count = 4; + output_3->qinfo = (struct csinn_quant_info *)(params_base + 2688); + output_3->quant_channel = 1; + struct csinn_relu_params *params_3 = csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_3->base.name = "relu_relu2_1/dw_7"; + csinn_relu_init(output_2, output_3, params_3); + struct csinn_tensor *output_4 = csinn_alloc_tensor(sess); + output_4->name = "output_4"; + output_4->dtype = CSINN_DTYPE_FLOAT16; + output_4->layout = CSINN_LAYOUT_NCHW; + output_4->dim[0] = 1; + output_4->dim[1] = 64; + output_4->dim[2] = 112; + output_4->dim[3] = 112; + output_4->dim_count = 4; + output_4->qinfo = (struct csinn_quant_info *)(params_base + 2712); + output_4->quant_channel = 1; + struct csinn_tensor *kernel_4 = csinn_alloc_tensor(sess); + kernel_4->name = "kernel_4"; + kernel_4->data = params_base + 2760; + kernel_4->is_const = 1; + kernel_4->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_4->dtype = CSINN_DTYPE_FLOAT16; + kernel_4->layout = CSINN_LAYOUT_OIHW; + kernel_4->dim[0] = 64; + kernel_4->dim[1] = 32; + kernel_4->dim[2] = 1; + kernel_4->dim[3] = 1; + kernel_4->dim_count = 4; + kernel_4->qinfo = (struct csinn_quant_info *)(params_base + 2736); + kernel_4->quant_channel = 1; + struct csinn_tensor *bias_4 = csinn_alloc_tensor(sess); + bias_4->name = "bias_4"; + bias_4->data = params_base + 6912; + bias_4->is_const = 1; + bias_4->dtype = CSINN_DTYPE_FLOAT16; + bias_4->layout = CSINN_LAYOUT_O; + bias_4->dim[0] = 64; + bias_4->dim_count = 1; + bias_4->qinfo = (struct csinn_quant_info *)(params_base + 6888); + bias_4->quant_channel = 1; + struct csinn_conv2d_params *params_4 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_4->group = 1; + params_4->stride_height = 1; + params_4->stride_width = 1; + params_4->dilation_height = 1; + params_4->dilation_width = 1; + params_4->conv_extra.kernel_tm = NULL; + params_4->conv_extra.conv_mode = CSINN_DIRECT; + params_4->pad_top = 0; + params_4->pad_left = 0; + params_4->pad_down = 0; + params_4->pad_right = 0; + params_4->base.name = "conv2d_conv2_1/sep_8_fuse_multiply_9_fuse_add_conv2_1/sep/bn_PART_0_10"; + csinn_conv2d_init(output_3, output_4, kernel_4, bias_4, params_4); + struct csinn_tensor *output_5 = csinn_alloc_tensor(sess); + output_5->name = "output_5"; + output_5->dtype = CSINN_DTYPE_FLOAT16; + output_5->layout = CSINN_LAYOUT_NCHW; + output_5->dim[0] = 1; + output_5->dim[1] = 64; + output_5->dim[2] = 112; + output_5->dim[3] = 112; + output_5->dim_count = 4; + output_5->qinfo = (struct csinn_quant_info *)(params_base + 7040); + output_5->quant_channel = 1; + struct csinn_relu_params *params_5 = csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_5->base.name = "relu_relu2_1/sep_11"; + csinn_relu_init(output_4, output_5, params_5); + struct csinn_tensor *output_6 = csinn_alloc_tensor(sess); + output_6->name = "output_6"; + output_6->dtype = CSINN_DTYPE_FLOAT16; + output_6->layout = CSINN_LAYOUT_NCHW; + output_6->dim[0] = 1; + output_6->dim[1] = 64; + output_6->dim[2] = 56; + output_6->dim[3] = 56; + output_6->dim_count = 4; + output_6->qinfo = (struct csinn_quant_info *)(params_base + 7064); + output_6->quant_channel = 1; + struct csinn_tensor *kernel_6 = csinn_alloc_tensor(sess); + kernel_6->name = "kernel_6"; + kernel_6->data = params_base + 7112; + kernel_6->is_const = 1; + kernel_6->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_6->dtype = CSINN_DTYPE_FLOAT16; + kernel_6->layout = CSINN_LAYOUT_O1HW; + kernel_6->dim[0] = 64; + kernel_6->dim[1] = 1; + kernel_6->dim[2] = 3; + kernel_6->dim[3] = 3; + kernel_6->dim_count = 4; + kernel_6->qinfo = (struct csinn_quant_info *)(params_base + 7088); + kernel_6->quant_channel = 1; + struct csinn_tensor *bias_6 = csinn_alloc_tensor(sess); + bias_6->name = "bias_6"; + bias_6->data = params_base + 8320; + bias_6->is_const = 1; + bias_6->dtype = CSINN_DTYPE_FLOAT16; + bias_6->layout = CSINN_LAYOUT_O; + bias_6->dim[0] = 64; + bias_6->dim_count = 1; + bias_6->qinfo = (struct csinn_quant_info *)(params_base + 8296); + bias_6->quant_channel = 1; + struct csinn_conv2d_params *params_6 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_6->group = 64; + params_6->stride_height = 2; + params_6->stride_width = 2; + params_6->dilation_height = 1; + params_6->dilation_width = 1; + params_6->conv_extra.kernel_tm = NULL; + params_6->conv_extra.conv_mode = CSINN_DIRECT; + params_6->pad_top = 1; + params_6->pad_left = 1; + params_6->pad_down = 1; + params_6->pad_right = 1; + params_6->base.name = "conv2d_conv2_2/dw_12_fuse_multiply_13_fuse_add_conv2_2/dw/bn_PART_0_14"; + csinn_conv2d_init(output_5, output_6, kernel_6, bias_6, params_6); + struct csinn_tensor *output_7 = csinn_alloc_tensor(sess); + output_7->name = "output_7"; + output_7->dtype = CSINN_DTYPE_FLOAT16; + output_7->layout = CSINN_LAYOUT_NCHW; + output_7->dim[0] = 1; + output_7->dim[1] = 64; + output_7->dim[2] = 56; + output_7->dim[3] = 56; + output_7->dim_count = 4; + output_7->qinfo = (struct csinn_quant_info *)(params_base + 8448); + output_7->quant_channel = 1; + struct csinn_relu_params *params_7 = csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_7->base.name = "relu_relu2_2/dw_15"; + csinn_relu_init(output_6, output_7, params_7); + struct csinn_tensor *output_8 = csinn_alloc_tensor(sess); + output_8->name = "output_8"; + output_8->dtype = CSINN_DTYPE_FLOAT16; + output_8->layout = CSINN_LAYOUT_NCHW; + output_8->dim[0] = 1; + output_8->dim[1] = 128; + output_8->dim[2] = 56; + output_8->dim[3] = 56; + output_8->dim_count = 4; + output_8->qinfo = (struct csinn_quant_info *)(params_base + 8472); + output_8->quant_channel = 1; + struct csinn_tensor *kernel_8 = csinn_alloc_tensor(sess); + kernel_8->name = "kernel_8"; + kernel_8->data = params_base + 8520; + kernel_8->is_const = 1; + kernel_8->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_8->dtype = CSINN_DTYPE_FLOAT16; + kernel_8->layout = CSINN_LAYOUT_OIHW; + kernel_8->dim[0] = 128; + kernel_8->dim[1] = 64; + kernel_8->dim[2] = 1; + kernel_8->dim[3] = 1; + kernel_8->dim_count = 4; + kernel_8->qinfo = (struct csinn_quant_info *)(params_base + 8496); + kernel_8->quant_channel = 1; + struct csinn_tensor *bias_8 = csinn_alloc_tensor(sess); + bias_8->name = "bias_8"; + bias_8->data = params_base + 24960; + bias_8->is_const = 1; + bias_8->dtype = CSINN_DTYPE_FLOAT16; + bias_8->layout = CSINN_LAYOUT_O; + bias_8->dim[0] = 128; + bias_8->dim_count = 1; + bias_8->qinfo = (struct csinn_quant_info *)(params_base + 24936); + bias_8->quant_channel = 1; + struct csinn_conv2d_params *params_8 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_8->group = 1; + params_8->stride_height = 1; + params_8->stride_width = 1; + params_8->dilation_height = 1; + params_8->dilation_width = 1; + params_8->conv_extra.kernel_tm = NULL; + params_8->conv_extra.conv_mode = CSINN_DIRECT; + params_8->pad_top = 0; + params_8->pad_left = 0; + params_8->pad_down = 0; + params_8->pad_right = 0; + params_8->base.name = + "conv2d_conv2_2/sep_16_fuse_multiply_17_fuse_add_conv2_2/sep/bn_PART_0_18"; + csinn_conv2d_init(output_7, output_8, kernel_8, bias_8, params_8); + struct csinn_tensor *output_9 = csinn_alloc_tensor(sess); + output_9->name = "output_9"; + output_9->dtype = CSINN_DTYPE_FLOAT16; + output_9->layout = CSINN_LAYOUT_NCHW; + output_9->dim[0] = 1; + output_9->dim[1] = 128; + output_9->dim[2] = 56; + output_9->dim[3] = 56; + output_9->dim_count = 4; + output_9->qinfo = (struct csinn_quant_info *)(params_base + 25216); + output_9->quant_channel = 1; + struct csinn_relu_params *params_9 = csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_9->base.name = "relu_relu2_2/sep_19"; + csinn_relu_init(output_8, output_9, params_9); + struct csinn_tensor *output_10 = csinn_alloc_tensor(sess); + output_10->name = "output_10"; + output_10->dtype = CSINN_DTYPE_FLOAT16; + output_10->layout = CSINN_LAYOUT_NCHW; + output_10->dim[0] = 1; + output_10->dim[1] = 128; + output_10->dim[2] = 56; + output_10->dim[3] = 56; + output_10->dim_count = 4; + output_10->qinfo = (struct csinn_quant_info *)(params_base + 25240); + output_10->quant_channel = 1; + struct csinn_tensor *kernel_10 = csinn_alloc_tensor(sess); + kernel_10->name = "kernel_10"; + kernel_10->data = params_base + 25288; + kernel_10->is_const = 1; + kernel_10->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_10->dtype = CSINN_DTYPE_FLOAT16; + kernel_10->layout = CSINN_LAYOUT_O1HW; + kernel_10->dim[0] = 128; + kernel_10->dim[1] = 1; + kernel_10->dim[2] = 3; + kernel_10->dim[3] = 3; + kernel_10->dim_count = 4; + kernel_10->qinfo = (struct csinn_quant_info *)(params_base + 25264); + kernel_10->quant_channel = 1; + struct csinn_tensor *bias_10 = csinn_alloc_tensor(sess); + bias_10->name = "bias_10"; + bias_10->data = params_base + 27648; + bias_10->is_const = 1; + bias_10->dtype = CSINN_DTYPE_FLOAT16; + bias_10->layout = CSINN_LAYOUT_O; + bias_10->dim[0] = 128; + bias_10->dim_count = 1; + bias_10->qinfo = (struct csinn_quant_info *)(params_base + 27624); + bias_10->quant_channel = 1; + struct csinn_conv2d_params *params_10 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_10->group = 128; + params_10->stride_height = 1; + params_10->stride_width = 1; + params_10->dilation_height = 1; + params_10->dilation_width = 1; + params_10->conv_extra.kernel_tm = NULL; + params_10->conv_extra.conv_mode = CSINN_DIRECT; + params_10->pad_top = 1; + params_10->pad_left = 1; + params_10->pad_down = 1; + params_10->pad_right = 1; + params_10->base.name = "conv2d_conv3_1/dw_20_fuse_multiply_21_fuse_add_conv3_1/dw/bn_PART_0_22"; + csinn_conv2d_init(output_9, output_10, kernel_10, bias_10, params_10); + struct csinn_tensor *output_11 = csinn_alloc_tensor(sess); + output_11->name = "output_11"; + output_11->dtype = CSINN_DTYPE_FLOAT16; + output_11->layout = CSINN_LAYOUT_NCHW; + output_11->dim[0] = 1; + output_11->dim[1] = 128; + output_11->dim[2] = 56; + output_11->dim[3] = 56; + output_11->dim_count = 4; + output_11->qinfo = (struct csinn_quant_info *)(params_base + 27904); + output_11->quant_channel = 1; + struct csinn_relu_params *params_11 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_11->base.name = "relu_relu3_1/dw_23"; + csinn_relu_init(output_10, output_11, params_11); + struct csinn_tensor *output_12 = csinn_alloc_tensor(sess); + output_12->name = "output_12"; + output_12->dtype = CSINN_DTYPE_FLOAT16; + output_12->layout = CSINN_LAYOUT_NCHW; + output_12->dim[0] = 1; + output_12->dim[1] = 128; + output_12->dim[2] = 56; + output_12->dim[3] = 56; + output_12->dim_count = 4; + output_12->qinfo = (struct csinn_quant_info *)(params_base + 27928); + output_12->quant_channel = 1; + struct csinn_tensor *kernel_12 = csinn_alloc_tensor(sess); + kernel_12->name = "kernel_12"; + kernel_12->data = params_base + 27976; + kernel_12->is_const = 1; + kernel_12->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_12->dtype = CSINN_DTYPE_FLOAT16; + kernel_12->layout = CSINN_LAYOUT_OIHW; + kernel_12->dim[0] = 128; + kernel_12->dim[1] = 128; + kernel_12->dim[2] = 1; + kernel_12->dim[3] = 1; + kernel_12->dim_count = 4; + kernel_12->qinfo = (struct csinn_quant_info *)(params_base + 27952); + kernel_12->quant_channel = 1; + struct csinn_tensor *bias_12 = csinn_alloc_tensor(sess); + bias_12->name = "bias_12"; + bias_12->data = params_base + 60800; + bias_12->is_const = 1; + bias_12->dtype = CSINN_DTYPE_FLOAT16; + bias_12->layout = CSINN_LAYOUT_O; + bias_12->dim[0] = 128; + bias_12->dim_count = 1; + bias_12->qinfo = (struct csinn_quant_info *)(params_base + 60776); + bias_12->quant_channel = 1; + struct csinn_conv2d_params *params_12 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_12->group = 1; + params_12->stride_height = 1; + params_12->stride_width = 1; + params_12->dilation_height = 1; + params_12->dilation_width = 1; + params_12->conv_extra.kernel_tm = NULL; + params_12->conv_extra.conv_mode = CSINN_DIRECT; + params_12->pad_top = 0; + params_12->pad_left = 0; + params_12->pad_down = 0; + params_12->pad_right = 0; + params_12->base.name = + "conv2d_conv3_1/sep_24_fuse_multiply_25_fuse_add_conv3_1/sep/bn_PART_0_26"; + csinn_conv2d_init(output_11, output_12, kernel_12, bias_12, params_12); + struct csinn_tensor *output_13 = csinn_alloc_tensor(sess); + output_13->name = "output_13"; + output_13->dtype = CSINN_DTYPE_FLOAT16; + output_13->layout = CSINN_LAYOUT_NCHW; + output_13->dim[0] = 1; + output_13->dim[1] = 128; + output_13->dim[2] = 56; + output_13->dim[3] = 56; + output_13->dim_count = 4; + output_13->qinfo = (struct csinn_quant_info *)(params_base + 61056); + output_13->quant_channel = 1; + struct csinn_relu_params *params_13 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_13->base.name = "relu_relu3_1/sep_27"; + csinn_relu_init(output_12, output_13, params_13); + struct csinn_tensor *output_14 = csinn_alloc_tensor(sess); + output_14->name = "output_14"; + output_14->dtype = CSINN_DTYPE_FLOAT16; + output_14->layout = CSINN_LAYOUT_NCHW; + output_14->dim[0] = 1; + output_14->dim[1] = 128; + output_14->dim[2] = 28; + output_14->dim[3] = 28; + output_14->dim_count = 4; + output_14->qinfo = (struct csinn_quant_info *)(params_base + 61080); + output_14->quant_channel = 1; + struct csinn_tensor *kernel_14 = csinn_alloc_tensor(sess); + kernel_14->name = "kernel_14"; + kernel_14->data = params_base + 61128; + kernel_14->is_const = 1; + kernel_14->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_14->dtype = CSINN_DTYPE_FLOAT16; + kernel_14->layout = CSINN_LAYOUT_O1HW; + kernel_14->dim[0] = 128; + kernel_14->dim[1] = 1; + kernel_14->dim[2] = 3; + kernel_14->dim[3] = 3; + kernel_14->dim_count = 4; + kernel_14->qinfo = (struct csinn_quant_info *)(params_base + 61104); + kernel_14->quant_channel = 1; + struct csinn_tensor *bias_14 = csinn_alloc_tensor(sess); + bias_14->name = "bias_14"; + bias_14->data = params_base + 63488; + bias_14->is_const = 1; + bias_14->dtype = CSINN_DTYPE_FLOAT16; + bias_14->layout = CSINN_LAYOUT_O; + bias_14->dim[0] = 128; + bias_14->dim_count = 1; + bias_14->qinfo = (struct csinn_quant_info *)(params_base + 63464); + bias_14->quant_channel = 1; + struct csinn_conv2d_params *params_14 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_14->group = 128; + params_14->stride_height = 2; + params_14->stride_width = 2; + params_14->dilation_height = 1; + params_14->dilation_width = 1; + params_14->conv_extra.kernel_tm = NULL; + params_14->conv_extra.conv_mode = CSINN_DIRECT; + params_14->pad_top = 1; + params_14->pad_left = 1; + params_14->pad_down = 1; + params_14->pad_right = 1; + params_14->base.name = "conv2d_conv3_2/dw_28_fuse_multiply_29_fuse_add_conv3_2/dw/bn_PART_0_30"; + csinn_conv2d_init(output_13, output_14, kernel_14, bias_14, params_14); + struct csinn_tensor *output_15 = csinn_alloc_tensor(sess); + output_15->name = "output_15"; + output_15->dtype = CSINN_DTYPE_FLOAT16; + output_15->layout = CSINN_LAYOUT_NCHW; + output_15->dim[0] = 1; + output_15->dim[1] = 128; + output_15->dim[2] = 28; + output_15->dim[3] = 28; + output_15->dim_count = 4; + output_15->qinfo = (struct csinn_quant_info *)(params_base + 63744); + output_15->quant_channel = 1; + struct csinn_relu_params *params_15 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_15->base.name = "relu_relu3_2/dw_31"; + csinn_relu_init(output_14, output_15, params_15); + struct csinn_tensor *output_16 = csinn_alloc_tensor(sess); + output_16->name = "output_16"; + output_16->dtype = CSINN_DTYPE_FLOAT16; + output_16->layout = CSINN_LAYOUT_NCHW; + output_16->dim[0] = 1; + output_16->dim[1] = 256; + output_16->dim[2] = 28; + output_16->dim[3] = 28; + output_16->dim_count = 4; + output_16->qinfo = (struct csinn_quant_info *)(params_base + 63768); + output_16->quant_channel = 1; + struct csinn_tensor *kernel_16 = csinn_alloc_tensor(sess); + kernel_16->name = "kernel_16"; + kernel_16->data = params_base + 63816; + kernel_16->is_const = 1; + kernel_16->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_16->dtype = CSINN_DTYPE_FLOAT16; + kernel_16->layout = CSINN_LAYOUT_OIHW; + kernel_16->dim[0] = 256; + kernel_16->dim[1] = 128; + kernel_16->dim[2] = 1; + kernel_16->dim[3] = 1; + kernel_16->dim_count = 4; + kernel_16->qinfo = (struct csinn_quant_info *)(params_base + 63792); + kernel_16->quant_channel = 1; + struct csinn_tensor *bias_16 = csinn_alloc_tensor(sess); + bias_16->name = "bias_16"; + bias_16->data = params_base + 129408; + bias_16->is_const = 1; + bias_16->dtype = CSINN_DTYPE_FLOAT16; + bias_16->layout = CSINN_LAYOUT_O; + bias_16->dim[0] = 256; + bias_16->dim_count = 1; + bias_16->qinfo = (struct csinn_quant_info *)(params_base + 129384); + bias_16->quant_channel = 1; + struct csinn_conv2d_params *params_16 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_16->group = 1; + params_16->stride_height = 1; + params_16->stride_width = 1; + params_16->dilation_height = 1; + params_16->dilation_width = 1; + params_16->conv_extra.kernel_tm = NULL; + params_16->conv_extra.conv_mode = CSINN_DIRECT; + params_16->pad_top = 0; + params_16->pad_left = 0; + params_16->pad_down = 0; + params_16->pad_right = 0; + params_16->base.name = + "conv2d_conv3_2/sep_32_fuse_multiply_33_fuse_add_conv3_2/sep/bn_PART_0_34"; + csinn_conv2d_init(output_15, output_16, kernel_16, bias_16, params_16); + struct csinn_tensor *output_17 = csinn_alloc_tensor(sess); + output_17->name = "output_17"; + output_17->dtype = CSINN_DTYPE_FLOAT16; + output_17->layout = CSINN_LAYOUT_NCHW; + output_17->dim[0] = 1; + output_17->dim[1] = 256; + output_17->dim[2] = 28; + output_17->dim[3] = 28; + output_17->dim_count = 4; + output_17->qinfo = (struct csinn_quant_info *)(params_base + 129920); + output_17->quant_channel = 1; + struct csinn_relu_params *params_17 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_17->base.name = "relu_relu3_2/sep_35"; + csinn_relu_init(output_16, output_17, params_17); + struct csinn_tensor *output_18 = csinn_alloc_tensor(sess); + output_18->name = "output_18"; + output_18->dtype = CSINN_DTYPE_FLOAT16; + output_18->layout = CSINN_LAYOUT_NCHW; + output_18->dim[0] = 1; + output_18->dim[1] = 256; + output_18->dim[2] = 28; + output_18->dim[3] = 28; + output_18->dim_count = 4; + output_18->qinfo = (struct csinn_quant_info *)(params_base + 129944); + output_18->quant_channel = 1; + struct csinn_tensor *kernel_18 = csinn_alloc_tensor(sess); + kernel_18->name = "kernel_18"; + kernel_18->data = params_base + 129992; + kernel_18->is_const = 1; + kernel_18->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_18->dtype = CSINN_DTYPE_FLOAT16; + kernel_18->layout = CSINN_LAYOUT_O1HW; + kernel_18->dim[0] = 256; + kernel_18->dim[1] = 1; + kernel_18->dim[2] = 3; + kernel_18->dim[3] = 3; + kernel_18->dim_count = 4; + kernel_18->qinfo = (struct csinn_quant_info *)(params_base + 129968); + kernel_18->quant_channel = 1; + struct csinn_tensor *bias_18 = csinn_alloc_tensor(sess); + bias_18->name = "bias_18"; + bias_18->data = params_base + 134656; + bias_18->is_const = 1; + bias_18->dtype = CSINN_DTYPE_FLOAT16; + bias_18->layout = CSINN_LAYOUT_O; + bias_18->dim[0] = 256; + bias_18->dim_count = 1; + bias_18->qinfo = (struct csinn_quant_info *)(params_base + 134632); + bias_18->quant_channel = 1; + struct csinn_conv2d_params *params_18 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_18->group = 256; + params_18->stride_height = 1; + params_18->stride_width = 1; + params_18->dilation_height = 1; + params_18->dilation_width = 1; + params_18->conv_extra.kernel_tm = NULL; + params_18->conv_extra.conv_mode = CSINN_DIRECT; + params_18->pad_top = 1; + params_18->pad_left = 1; + params_18->pad_down = 1; + params_18->pad_right = 1; + params_18->base.name = "conv2d_conv4_1/dw_36_fuse_multiply_37_fuse_add_conv4_1/dw/bn_PART_0_38"; + csinn_conv2d_init(output_17, output_18, kernel_18, bias_18, params_18); + struct csinn_tensor *output_19 = csinn_alloc_tensor(sess); + output_19->name = "output_19"; + output_19->dtype = CSINN_DTYPE_FLOAT16; + output_19->layout = CSINN_LAYOUT_NCHW; + output_19->dim[0] = 1; + output_19->dim[1] = 256; + output_19->dim[2] = 28; + output_19->dim[3] = 28; + output_19->dim_count = 4; + output_19->qinfo = (struct csinn_quant_info *)(params_base + 135168); + output_19->quant_channel = 1; + struct csinn_relu_params *params_19 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_19->base.name = "relu_relu4_1/dw_39"; + csinn_relu_init(output_18, output_19, params_19); + struct csinn_tensor *output_20 = csinn_alloc_tensor(sess); + output_20->name = "output_20"; + output_20->dtype = CSINN_DTYPE_FLOAT16; + output_20->layout = CSINN_LAYOUT_NCHW; + output_20->dim[0] = 1; + output_20->dim[1] = 256; + output_20->dim[2] = 28; + output_20->dim[3] = 28; + output_20->dim_count = 4; + output_20->qinfo = (struct csinn_quant_info *)(params_base + 135192); + output_20->quant_channel = 1; + struct csinn_tensor *kernel_20 = csinn_alloc_tensor(sess); + kernel_20->name = "kernel_20"; + kernel_20->data = params_base + 135240; + kernel_20->is_const = 1; + kernel_20->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_20->dtype = CSINN_DTYPE_FLOAT16; + kernel_20->layout = CSINN_LAYOUT_OIHW; + kernel_20->dim[0] = 256; + kernel_20->dim[1] = 256; + kernel_20->dim[2] = 1; + kernel_20->dim[3] = 1; + kernel_20->dim_count = 4; + kernel_20->qinfo = (struct csinn_quant_info *)(params_base + 135216); + kernel_20->quant_channel = 1; + struct csinn_tensor *bias_20 = csinn_alloc_tensor(sess); + bias_20->name = "bias_20"; + bias_20->data = params_base + 266368; + bias_20->is_const = 1; + bias_20->dtype = CSINN_DTYPE_FLOAT16; + bias_20->layout = CSINN_LAYOUT_O; + bias_20->dim[0] = 256; + bias_20->dim_count = 1; + bias_20->qinfo = (struct csinn_quant_info *)(params_base + 266344); + bias_20->quant_channel = 1; + struct csinn_conv2d_params *params_20 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_20->group = 1; + params_20->stride_height = 1; + params_20->stride_width = 1; + params_20->dilation_height = 1; + params_20->dilation_width = 1; + params_20->conv_extra.kernel_tm = NULL; + params_20->conv_extra.conv_mode = CSINN_DIRECT; + params_20->pad_top = 0; + params_20->pad_left = 0; + params_20->pad_down = 0; + params_20->pad_right = 0; + params_20->base.name = + "conv2d_conv4_1/sep_40_fuse_multiply_41_fuse_add_conv4_1/sep/bn_PART_0_42"; + csinn_conv2d_init(output_19, output_20, kernel_20, bias_20, params_20); + struct csinn_tensor *output_21 = csinn_alloc_tensor(sess); + output_21->name = "output_21"; + output_21->dtype = CSINN_DTYPE_FLOAT16; + output_21->layout = CSINN_LAYOUT_NCHW; + output_21->dim[0] = 1; + output_21->dim[1] = 256; + output_21->dim[2] = 28; + output_21->dim[3] = 28; + output_21->dim_count = 4; + output_21->qinfo = (struct csinn_quant_info *)(params_base + 266880); + output_21->quant_channel = 1; + struct csinn_relu_params *params_21 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_21->base.name = "relu_relu4_1/sep_43"; + csinn_relu_init(output_20, output_21, params_21); + struct csinn_tensor *output_22 = csinn_alloc_tensor(sess); + output_22->name = "output_22"; + output_22->dtype = CSINN_DTYPE_FLOAT16; + output_22->layout = CSINN_LAYOUT_NCHW; + output_22->dim[0] = 1; + output_22->dim[1] = 256; + output_22->dim[2] = 14; + output_22->dim[3] = 14; + output_22->dim_count = 4; + output_22->qinfo = (struct csinn_quant_info *)(params_base + 266904); + output_22->quant_channel = 1; + struct csinn_tensor *kernel_22 = csinn_alloc_tensor(sess); + kernel_22->name = "kernel_22"; + kernel_22->data = params_base + 266952; + kernel_22->is_const = 1; + kernel_22->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_22->dtype = CSINN_DTYPE_FLOAT16; + kernel_22->layout = CSINN_LAYOUT_O1HW; + kernel_22->dim[0] = 256; + kernel_22->dim[1] = 1; + kernel_22->dim[2] = 3; + kernel_22->dim[3] = 3; + kernel_22->dim_count = 4; + kernel_22->qinfo = (struct csinn_quant_info *)(params_base + 266928); + kernel_22->quant_channel = 1; + struct csinn_tensor *bias_22 = csinn_alloc_tensor(sess); + bias_22->name = "bias_22"; + bias_22->data = params_base + 271616; + bias_22->is_const = 1; + bias_22->dtype = CSINN_DTYPE_FLOAT16; + bias_22->layout = CSINN_LAYOUT_O; + bias_22->dim[0] = 256; + bias_22->dim_count = 1; + bias_22->qinfo = (struct csinn_quant_info *)(params_base + 271592); + bias_22->quant_channel = 1; + struct csinn_conv2d_params *params_22 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_22->group = 256; + params_22->stride_height = 2; + params_22->stride_width = 2; + params_22->dilation_height = 1; + params_22->dilation_width = 1; + params_22->conv_extra.kernel_tm = NULL; + params_22->conv_extra.conv_mode = CSINN_DIRECT; + params_22->pad_top = 1; + params_22->pad_left = 1; + params_22->pad_down = 1; + params_22->pad_right = 1; + params_22->base.name = "conv2d_conv4_2/dw_44_fuse_multiply_45_fuse_add_conv4_2/dw/bn_PART_0_46"; + csinn_conv2d_init(output_21, output_22, kernel_22, bias_22, params_22); + struct csinn_tensor *output_23 = csinn_alloc_tensor(sess); + output_23->name = "output_23"; + output_23->dtype = CSINN_DTYPE_FLOAT16; + output_23->layout = CSINN_LAYOUT_NCHW; + output_23->dim[0] = 1; + output_23->dim[1] = 256; + output_23->dim[2] = 14; + output_23->dim[3] = 14; + output_23->dim_count = 4; + output_23->qinfo = (struct csinn_quant_info *)(params_base + 272128); + output_23->quant_channel = 1; + struct csinn_relu_params *params_23 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_23->base.name = "relu_relu4_2/dw_47"; + csinn_relu_init(output_22, output_23, params_23); + struct csinn_tensor *output_24 = csinn_alloc_tensor(sess); + output_24->name = "output_24"; + output_24->dtype = CSINN_DTYPE_FLOAT16; + output_24->layout = CSINN_LAYOUT_NCHW; + output_24->dim[0] = 1; + output_24->dim[1] = 512; + output_24->dim[2] = 14; + output_24->dim[3] = 14; + output_24->dim_count = 4; + output_24->qinfo = (struct csinn_quant_info *)(params_base + 272152); + output_24->quant_channel = 1; + struct csinn_tensor *kernel_24 = csinn_alloc_tensor(sess); + kernel_24->name = "kernel_24"; + kernel_24->data = params_base + 272200; + kernel_24->is_const = 1; + kernel_24->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_24->dtype = CSINN_DTYPE_FLOAT16; + kernel_24->layout = CSINN_LAYOUT_OIHW; + kernel_24->dim[0] = 512; + kernel_24->dim[1] = 256; + kernel_24->dim[2] = 1; + kernel_24->dim[3] = 1; + kernel_24->dim_count = 4; + kernel_24->qinfo = (struct csinn_quant_info *)(params_base + 272176); + kernel_24->quant_channel = 1; + struct csinn_tensor *bias_24 = csinn_alloc_tensor(sess); + bias_24->name = "bias_24"; + bias_24->data = params_base + 534400; + bias_24->is_const = 1; + bias_24->dtype = CSINN_DTYPE_FLOAT16; + bias_24->layout = CSINN_LAYOUT_O; + bias_24->dim[0] = 512; + bias_24->dim_count = 1; + bias_24->qinfo = (struct csinn_quant_info *)(params_base + 534376); + bias_24->quant_channel = 1; + struct csinn_conv2d_params *params_24 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_24->group = 1; + params_24->stride_height = 1; + params_24->stride_width = 1; + params_24->dilation_height = 1; + params_24->dilation_width = 1; + params_24->conv_extra.kernel_tm = NULL; + params_24->conv_extra.conv_mode = CSINN_DIRECT; + params_24->pad_top = 0; + params_24->pad_left = 0; + params_24->pad_down = 0; + params_24->pad_right = 0; + params_24->base.name = + "conv2d_conv4_2/sep_48_fuse_multiply_49_fuse_add_conv4_2/sep/bn_PART_0_50"; + csinn_conv2d_init(output_23, output_24, kernel_24, bias_24, params_24); + struct csinn_tensor *output_25 = csinn_alloc_tensor(sess); + output_25->name = "output_25"; + output_25->dtype = CSINN_DTYPE_FLOAT16; + output_25->layout = CSINN_LAYOUT_NCHW; + output_25->dim[0] = 1; + output_25->dim[1] = 512; + output_25->dim[2] = 14; + output_25->dim[3] = 14; + output_25->dim_count = 4; + output_25->qinfo = (struct csinn_quant_info *)(params_base + 535424); + output_25->quant_channel = 1; + struct csinn_relu_params *params_25 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_25->base.name = "relu_relu4_2/sep_51"; + csinn_relu_init(output_24, output_25, params_25); + struct csinn_tensor *output_26 = csinn_alloc_tensor(sess); + output_26->name = "output_26"; + output_26->dtype = CSINN_DTYPE_FLOAT16; + output_26->layout = CSINN_LAYOUT_NCHW; + output_26->dim[0] = 1; + output_26->dim[1] = 512; + output_26->dim[2] = 14; + output_26->dim[3] = 14; + output_26->dim_count = 4; + output_26->qinfo = (struct csinn_quant_info *)(params_base + 535448); + output_26->quant_channel = 1; + struct csinn_tensor *kernel_26 = csinn_alloc_tensor(sess); + kernel_26->name = "kernel_26"; + kernel_26->data = params_base + 535496; + kernel_26->is_const = 1; + kernel_26->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_26->dtype = CSINN_DTYPE_FLOAT16; + kernel_26->layout = CSINN_LAYOUT_O1HW; + kernel_26->dim[0] = 512; + kernel_26->dim[1] = 1; + kernel_26->dim[2] = 3; + kernel_26->dim[3] = 3; + kernel_26->dim_count = 4; + kernel_26->qinfo = (struct csinn_quant_info *)(params_base + 535472); + kernel_26->quant_channel = 1; + struct csinn_tensor *bias_26 = csinn_alloc_tensor(sess); + bias_26->name = "bias_26"; + bias_26->data = params_base + 544768; + bias_26->is_const = 1; + bias_26->dtype = CSINN_DTYPE_FLOAT16; + bias_26->layout = CSINN_LAYOUT_O; + bias_26->dim[0] = 512; + bias_26->dim_count = 1; + bias_26->qinfo = (struct csinn_quant_info *)(params_base + 544744); + bias_26->quant_channel = 1; + struct csinn_conv2d_params *params_26 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_26->group = 512; + params_26->stride_height = 1; + params_26->stride_width = 1; + params_26->dilation_height = 1; + params_26->dilation_width = 1; + params_26->conv_extra.kernel_tm = NULL; + params_26->conv_extra.conv_mode = CSINN_DIRECT; + params_26->pad_top = 1; + params_26->pad_left = 1; + params_26->pad_down = 1; + params_26->pad_right = 1; + params_26->base.name = "conv2d_conv5_1/dw_52_fuse_multiply_53_fuse_add_conv5_1/dw/bn_PART_0_54"; + csinn_conv2d_init(output_25, output_26, kernel_26, bias_26, params_26); + struct csinn_tensor *output_27 = csinn_alloc_tensor(sess); + output_27->name = "output_27"; + output_27->dtype = CSINN_DTYPE_FLOAT16; + output_27->layout = CSINN_LAYOUT_NCHW; + output_27->dim[0] = 1; + output_27->dim[1] = 512; + output_27->dim[2] = 14; + output_27->dim[3] = 14; + output_27->dim_count = 4; + output_27->qinfo = (struct csinn_quant_info *)(params_base + 545792); + output_27->quant_channel = 1; + struct csinn_relu_params *params_27 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_27->base.name = "relu_relu5_1/dw_55"; + csinn_relu_init(output_26, output_27, params_27); + struct csinn_tensor *output_28 = csinn_alloc_tensor(sess); + output_28->name = "output_28"; + output_28->dtype = CSINN_DTYPE_FLOAT16; + output_28->layout = CSINN_LAYOUT_NCHW; + output_28->dim[0] = 1; + output_28->dim[1] = 512; + output_28->dim[2] = 14; + output_28->dim[3] = 14; + output_28->dim_count = 4; + output_28->qinfo = (struct csinn_quant_info *)(params_base + 545816); + output_28->quant_channel = 1; + struct csinn_tensor *kernel_28 = csinn_alloc_tensor(sess); + kernel_28->name = "kernel_28"; + kernel_28->data = params_base + 545864; + kernel_28->is_const = 1; + kernel_28->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_28->dtype = CSINN_DTYPE_FLOAT16; + kernel_28->layout = CSINN_LAYOUT_OIHW; + kernel_28->dim[0] = 512; + kernel_28->dim[1] = 512; + kernel_28->dim[2] = 1; + kernel_28->dim[3] = 1; + kernel_28->dim_count = 4; + kernel_28->qinfo = (struct csinn_quant_info *)(params_base + 545840); + kernel_28->quant_channel = 1; + struct csinn_tensor *bias_28 = csinn_alloc_tensor(sess); + bias_28->name = "bias_28"; + bias_28->data = params_base + 1070208; + bias_28->is_const = 1; + bias_28->dtype = CSINN_DTYPE_FLOAT16; + bias_28->layout = CSINN_LAYOUT_O; + bias_28->dim[0] = 512; + bias_28->dim_count = 1; + bias_28->qinfo = (struct csinn_quant_info *)(params_base + 1070184); + bias_28->quant_channel = 1; + struct csinn_conv2d_params *params_28 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_28->group = 1; + params_28->stride_height = 1; + params_28->stride_width = 1; + params_28->dilation_height = 1; + params_28->dilation_width = 1; + params_28->conv_extra.kernel_tm = NULL; + params_28->conv_extra.conv_mode = CSINN_DIRECT; + params_28->pad_top = 0; + params_28->pad_left = 0; + params_28->pad_down = 0; + params_28->pad_right = 0; + params_28->base.name = + "conv2d_conv5_1/sep_56_fuse_multiply_57_fuse_add_conv5_1/sep/bn_PART_0_58"; + csinn_conv2d_init(output_27, output_28, kernel_28, bias_28, params_28); + struct csinn_tensor *output_29 = csinn_alloc_tensor(sess); + output_29->name = "output_29"; + output_29->dtype = CSINN_DTYPE_FLOAT16; + output_29->layout = CSINN_LAYOUT_NCHW; + output_29->dim[0] = 1; + output_29->dim[1] = 512; + output_29->dim[2] = 14; + output_29->dim[3] = 14; + output_29->dim_count = 4; + output_29->qinfo = (struct csinn_quant_info *)(params_base + 1071232); + output_29->quant_channel = 1; + struct csinn_relu_params *params_29 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_29->base.name = "relu_relu5_1/sep_59"; + csinn_relu_init(output_28, output_29, params_29); + struct csinn_tensor *output_30 = csinn_alloc_tensor(sess); + output_30->name = "output_30"; + output_30->dtype = CSINN_DTYPE_FLOAT16; + output_30->layout = CSINN_LAYOUT_NCHW; + output_30->dim[0] = 1; + output_30->dim[1] = 512; + output_30->dim[2] = 14; + output_30->dim[3] = 14; + output_30->dim_count = 4; + output_30->qinfo = (struct csinn_quant_info *)(params_base + 1071256); + output_30->quant_channel = 1; + struct csinn_tensor *kernel_30 = csinn_alloc_tensor(sess); + kernel_30->name = "kernel_30"; + kernel_30->data = params_base + 1071304; + kernel_30->is_const = 1; + kernel_30->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_30->dtype = CSINN_DTYPE_FLOAT16; + kernel_30->layout = CSINN_LAYOUT_O1HW; + kernel_30->dim[0] = 512; + kernel_30->dim[1] = 1; + kernel_30->dim[2] = 3; + kernel_30->dim[3] = 3; + kernel_30->dim_count = 4; + kernel_30->qinfo = (struct csinn_quant_info *)(params_base + 1071280); + kernel_30->quant_channel = 1; + struct csinn_tensor *bias_30 = csinn_alloc_tensor(sess); + bias_30->name = "bias_30"; + bias_30->data = params_base + 1080576; + bias_30->is_const = 1; + bias_30->dtype = CSINN_DTYPE_FLOAT16; + bias_30->layout = CSINN_LAYOUT_O; + bias_30->dim[0] = 512; + bias_30->dim_count = 1; + bias_30->qinfo = (struct csinn_quant_info *)(params_base + 1080552); + bias_30->quant_channel = 1; + struct csinn_conv2d_params *params_30 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_30->group = 512; + params_30->stride_height = 1; + params_30->stride_width = 1; + params_30->dilation_height = 1; + params_30->dilation_width = 1; + params_30->conv_extra.kernel_tm = NULL; + params_30->conv_extra.conv_mode = CSINN_DIRECT; + params_30->pad_top = 1; + params_30->pad_left = 1; + params_30->pad_down = 1; + params_30->pad_right = 1; + params_30->base.name = "conv2d_conv5_2/dw_60_fuse_multiply_61_fuse_add_conv5_2/dw/bn_PART_0_62"; + csinn_conv2d_init(output_29, output_30, kernel_30, bias_30, params_30); + struct csinn_tensor *output_31 = csinn_alloc_tensor(sess); + output_31->name = "output_31"; + output_31->dtype = CSINN_DTYPE_FLOAT16; + output_31->layout = CSINN_LAYOUT_NCHW; + output_31->dim[0] = 1; + output_31->dim[1] = 512; + output_31->dim[2] = 14; + output_31->dim[3] = 14; + output_31->dim_count = 4; + output_31->qinfo = (struct csinn_quant_info *)(params_base + 1081600); + output_31->quant_channel = 1; + struct csinn_relu_params *params_31 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_31->base.name = "relu_relu5_2/dw_63"; + csinn_relu_init(output_30, output_31, params_31); + struct csinn_tensor *output_32 = csinn_alloc_tensor(sess); + output_32->name = "output_32"; + output_32->dtype = CSINN_DTYPE_FLOAT16; + output_32->layout = CSINN_LAYOUT_NCHW; + output_32->dim[0] = 1; + output_32->dim[1] = 512; + output_32->dim[2] = 14; + output_32->dim[3] = 14; + output_32->dim_count = 4; + output_32->qinfo = (struct csinn_quant_info *)(params_base + 1081624); + output_32->quant_channel = 1; + struct csinn_tensor *kernel_32 = csinn_alloc_tensor(sess); + kernel_32->name = "kernel_32"; + kernel_32->data = params_base + 1081672; + kernel_32->is_const = 1; + kernel_32->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_32->dtype = CSINN_DTYPE_FLOAT16; + kernel_32->layout = CSINN_LAYOUT_OIHW; + kernel_32->dim[0] = 512; + kernel_32->dim[1] = 512; + kernel_32->dim[2] = 1; + kernel_32->dim[3] = 1; + kernel_32->dim_count = 4; + kernel_32->qinfo = (struct csinn_quant_info *)(params_base + 1081648); + kernel_32->quant_channel = 1; + struct csinn_tensor *bias_32 = csinn_alloc_tensor(sess); + bias_32->name = "bias_32"; + bias_32->data = params_base + 1606016; + bias_32->is_const = 1; + bias_32->dtype = CSINN_DTYPE_FLOAT16; + bias_32->layout = CSINN_LAYOUT_O; + bias_32->dim[0] = 512; + bias_32->dim_count = 1; + bias_32->qinfo = (struct csinn_quant_info *)(params_base + 1605992); + bias_32->quant_channel = 1; + struct csinn_conv2d_params *params_32 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_32->group = 1; + params_32->stride_height = 1; + params_32->stride_width = 1; + params_32->dilation_height = 1; + params_32->dilation_width = 1; + params_32->conv_extra.kernel_tm = NULL; + params_32->conv_extra.conv_mode = CSINN_DIRECT; + params_32->pad_top = 0; + params_32->pad_left = 0; + params_32->pad_down = 0; + params_32->pad_right = 0; + params_32->base.name = + "conv2d_conv5_2/sep_64_fuse_multiply_65_fuse_add_conv5_2/sep/bn_PART_0_66"; + csinn_conv2d_init(output_31, output_32, kernel_32, bias_32, params_32); + struct csinn_tensor *output_33 = csinn_alloc_tensor(sess); + output_33->name = "output_33"; + output_33->dtype = CSINN_DTYPE_FLOAT16; + output_33->layout = CSINN_LAYOUT_NCHW; + output_33->dim[0] = 1; + output_33->dim[1] = 512; + output_33->dim[2] = 14; + output_33->dim[3] = 14; + output_33->dim_count = 4; + output_33->qinfo = (struct csinn_quant_info *)(params_base + 1607040); + output_33->quant_channel = 1; + struct csinn_relu_params *params_33 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_33->base.name = "relu_relu5_2/sep_67"; + csinn_relu_init(output_32, output_33, params_33); + struct csinn_tensor *output_34 = csinn_alloc_tensor(sess); + output_34->name = "output_34"; + output_34->dtype = CSINN_DTYPE_FLOAT16; + output_34->layout = CSINN_LAYOUT_NCHW; + output_34->dim[0] = 1; + output_34->dim[1] = 512; + output_34->dim[2] = 14; + output_34->dim[3] = 14; + output_34->dim_count = 4; + output_34->qinfo = (struct csinn_quant_info *)(params_base + 1607064); + output_34->quant_channel = 1; + struct csinn_tensor *kernel_34 = csinn_alloc_tensor(sess); + kernel_34->name = "kernel_34"; + kernel_34->data = params_base + 1607112; + kernel_34->is_const = 1; + kernel_34->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_34->dtype = CSINN_DTYPE_FLOAT16; + kernel_34->layout = CSINN_LAYOUT_O1HW; + kernel_34->dim[0] = 512; + kernel_34->dim[1] = 1; + kernel_34->dim[2] = 3; + kernel_34->dim[3] = 3; + kernel_34->dim_count = 4; + kernel_34->qinfo = (struct csinn_quant_info *)(params_base + 1607088); + kernel_34->quant_channel = 1; + struct csinn_tensor *bias_34 = csinn_alloc_tensor(sess); + bias_34->name = "bias_34"; + bias_34->data = params_base + 1616384; + bias_34->is_const = 1; + bias_34->dtype = CSINN_DTYPE_FLOAT16; + bias_34->layout = CSINN_LAYOUT_O; + bias_34->dim[0] = 512; + bias_34->dim_count = 1; + bias_34->qinfo = (struct csinn_quant_info *)(params_base + 1616360); + bias_34->quant_channel = 1; + struct csinn_conv2d_params *params_34 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_34->group = 512; + params_34->stride_height = 1; + params_34->stride_width = 1; + params_34->dilation_height = 1; + params_34->dilation_width = 1; + params_34->conv_extra.kernel_tm = NULL; + params_34->conv_extra.conv_mode = CSINN_DIRECT; + params_34->pad_top = 1; + params_34->pad_left = 1; + params_34->pad_down = 1; + params_34->pad_right = 1; + params_34->base.name = "conv2d_conv5_3/dw_68_fuse_multiply_69_fuse_add_conv5_3/dw/bn_PART_0_70"; + csinn_conv2d_init(output_33, output_34, kernel_34, bias_34, params_34); + struct csinn_tensor *output_35 = csinn_alloc_tensor(sess); + output_35->name = "output_35"; + output_35->dtype = CSINN_DTYPE_FLOAT16; + output_35->layout = CSINN_LAYOUT_NCHW; + output_35->dim[0] = 1; + output_35->dim[1] = 512; + output_35->dim[2] = 14; + output_35->dim[3] = 14; + output_35->dim_count = 4; + output_35->qinfo = (struct csinn_quant_info *)(params_base + 1617408); + output_35->quant_channel = 1; + struct csinn_relu_params *params_35 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_35->base.name = "relu_relu5_3/dw_71"; + csinn_relu_init(output_34, output_35, params_35); + struct csinn_tensor *output_36 = csinn_alloc_tensor(sess); + output_36->name = "output_36"; + output_36->dtype = CSINN_DTYPE_FLOAT16; + output_36->layout = CSINN_LAYOUT_NCHW; + output_36->dim[0] = 1; + output_36->dim[1] = 512; + output_36->dim[2] = 14; + output_36->dim[3] = 14; + output_36->dim_count = 4; + output_36->qinfo = (struct csinn_quant_info *)(params_base + 1617432); + output_36->quant_channel = 1; + struct csinn_tensor *kernel_36 = csinn_alloc_tensor(sess); + kernel_36->name = "kernel_36"; + kernel_36->data = params_base + 1617480; + kernel_36->is_const = 1; + kernel_36->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_36->dtype = CSINN_DTYPE_FLOAT16; + kernel_36->layout = CSINN_LAYOUT_OIHW; + kernel_36->dim[0] = 512; + kernel_36->dim[1] = 512; + kernel_36->dim[2] = 1; + kernel_36->dim[3] = 1; + kernel_36->dim_count = 4; + kernel_36->qinfo = (struct csinn_quant_info *)(params_base + 1617456); + kernel_36->quant_channel = 1; + struct csinn_tensor *bias_36 = csinn_alloc_tensor(sess); + bias_36->name = "bias_36"; + bias_36->data = params_base + 2141824; + bias_36->is_const = 1; + bias_36->dtype = CSINN_DTYPE_FLOAT16; + bias_36->layout = CSINN_LAYOUT_O; + bias_36->dim[0] = 512; + bias_36->dim_count = 1; + bias_36->qinfo = (struct csinn_quant_info *)(params_base + 2141800); + bias_36->quant_channel = 1; + struct csinn_conv2d_params *params_36 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_36->group = 1; + params_36->stride_height = 1; + params_36->stride_width = 1; + params_36->dilation_height = 1; + params_36->dilation_width = 1; + params_36->conv_extra.kernel_tm = NULL; + params_36->conv_extra.conv_mode = CSINN_DIRECT; + params_36->pad_top = 0; + params_36->pad_left = 0; + params_36->pad_down = 0; + params_36->pad_right = 0; + params_36->base.name = + "conv2d_conv5_3/sep_72_fuse_multiply_73_fuse_add_conv5_3/sep/bn_PART_0_74"; + csinn_conv2d_init(output_35, output_36, kernel_36, bias_36, params_36); + struct csinn_tensor *output_37 = csinn_alloc_tensor(sess); + output_37->name = "output_37"; + output_37->dtype = CSINN_DTYPE_FLOAT16; + output_37->layout = CSINN_LAYOUT_NCHW; + output_37->dim[0] = 1; + output_37->dim[1] = 512; + output_37->dim[2] = 14; + output_37->dim[3] = 14; + output_37->dim_count = 4; + output_37->qinfo = (struct csinn_quant_info *)(params_base + 2142848); + output_37->quant_channel = 1; + struct csinn_relu_params *params_37 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_37->base.name = "relu_relu5_3/sep_75"; + csinn_relu_init(output_36, output_37, params_37); + struct csinn_tensor *output_38 = csinn_alloc_tensor(sess); + output_38->name = "output_38"; + output_38->dtype = CSINN_DTYPE_FLOAT16; + output_38->layout = CSINN_LAYOUT_NCHW; + output_38->dim[0] = 1; + output_38->dim[1] = 512; + output_38->dim[2] = 14; + output_38->dim[3] = 14; + output_38->dim_count = 4; + output_38->qinfo = (struct csinn_quant_info *)(params_base + 2142872); + output_38->quant_channel = 1; + struct csinn_tensor *kernel_38 = csinn_alloc_tensor(sess); + kernel_38->name = "kernel_38"; + kernel_38->data = params_base + 2142920; + kernel_38->is_const = 1; + kernel_38->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_38->dtype = CSINN_DTYPE_FLOAT16; + kernel_38->layout = CSINN_LAYOUT_O1HW; + kernel_38->dim[0] = 512; + kernel_38->dim[1] = 1; + kernel_38->dim[2] = 3; + kernel_38->dim[3] = 3; + kernel_38->dim_count = 4; + kernel_38->qinfo = (struct csinn_quant_info *)(params_base + 2142896); + kernel_38->quant_channel = 1; + struct csinn_tensor *bias_38 = csinn_alloc_tensor(sess); + bias_38->name = "bias_38"; + bias_38->data = params_base + 2152192; + bias_38->is_const = 1; + bias_38->dtype = CSINN_DTYPE_FLOAT16; + bias_38->layout = CSINN_LAYOUT_O; + bias_38->dim[0] = 512; + bias_38->dim_count = 1; + bias_38->qinfo = (struct csinn_quant_info *)(params_base + 2152168); + bias_38->quant_channel = 1; + struct csinn_conv2d_params *params_38 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_38->group = 512; + params_38->stride_height = 1; + params_38->stride_width = 1; + params_38->dilation_height = 1; + params_38->dilation_width = 1; + params_38->conv_extra.kernel_tm = NULL; + params_38->conv_extra.conv_mode = CSINN_DIRECT; + params_38->pad_top = 1; + params_38->pad_left = 1; + params_38->pad_down = 1; + params_38->pad_right = 1; + params_38->base.name = "conv2d_conv5_4/dw_76_fuse_multiply_77_fuse_add_conv5_4/dw/bn_PART_0_78"; + csinn_conv2d_init(output_37, output_38, kernel_38, bias_38, params_38); + struct csinn_tensor *output_39 = csinn_alloc_tensor(sess); + output_39->name = "output_39"; + output_39->dtype = CSINN_DTYPE_FLOAT16; + output_39->layout = CSINN_LAYOUT_NCHW; + output_39->dim[0] = 1; + output_39->dim[1] = 512; + output_39->dim[2] = 14; + output_39->dim[3] = 14; + output_39->dim_count = 4; + output_39->qinfo = (struct csinn_quant_info *)(params_base + 2153216); + output_39->quant_channel = 1; + struct csinn_relu_params *params_39 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_39->base.name = "relu_relu5_4/dw_79"; + csinn_relu_init(output_38, output_39, params_39); + struct csinn_tensor *output_40 = csinn_alloc_tensor(sess); + output_40->name = "output_40"; + output_40->dtype = CSINN_DTYPE_FLOAT16; + output_40->layout = CSINN_LAYOUT_NCHW; + output_40->dim[0] = 1; + output_40->dim[1] = 512; + output_40->dim[2] = 14; + output_40->dim[3] = 14; + output_40->dim_count = 4; + output_40->qinfo = (struct csinn_quant_info *)(params_base + 2153240); + output_40->quant_channel = 1; + struct csinn_tensor *kernel_40 = csinn_alloc_tensor(sess); + kernel_40->name = "kernel_40"; + kernel_40->data = params_base + 2153288; + kernel_40->is_const = 1; + kernel_40->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_40->dtype = CSINN_DTYPE_FLOAT16; + kernel_40->layout = CSINN_LAYOUT_OIHW; + kernel_40->dim[0] = 512; + kernel_40->dim[1] = 512; + kernel_40->dim[2] = 1; + kernel_40->dim[3] = 1; + kernel_40->dim_count = 4; + kernel_40->qinfo = (struct csinn_quant_info *)(params_base + 2153264); + kernel_40->quant_channel = 1; + struct csinn_tensor *bias_40 = csinn_alloc_tensor(sess); + bias_40->name = "bias_40"; + bias_40->data = params_base + 2677632; + bias_40->is_const = 1; + bias_40->dtype = CSINN_DTYPE_FLOAT16; + bias_40->layout = CSINN_LAYOUT_O; + bias_40->dim[0] = 512; + bias_40->dim_count = 1; + bias_40->qinfo = (struct csinn_quant_info *)(params_base + 2677608); + bias_40->quant_channel = 1; + struct csinn_conv2d_params *params_40 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_40->group = 1; + params_40->stride_height = 1; + params_40->stride_width = 1; + params_40->dilation_height = 1; + params_40->dilation_width = 1; + params_40->conv_extra.kernel_tm = NULL; + params_40->conv_extra.conv_mode = CSINN_DIRECT; + params_40->pad_top = 0; + params_40->pad_left = 0; + params_40->pad_down = 0; + params_40->pad_right = 0; + params_40->base.name = + "conv2d_conv5_4/sep_80_fuse_multiply_81_fuse_add_conv5_4/sep/bn_PART_0_82"; + csinn_conv2d_init(output_39, output_40, kernel_40, bias_40, params_40); + struct csinn_tensor *output_41 = csinn_alloc_tensor(sess); + output_41->name = "output_41"; + output_41->dtype = CSINN_DTYPE_FLOAT16; + output_41->layout = CSINN_LAYOUT_NCHW; + output_41->dim[0] = 1; + output_41->dim[1] = 512; + output_41->dim[2] = 14; + output_41->dim[3] = 14; + output_41->dim_count = 4; + output_41->qinfo = (struct csinn_quant_info *)(params_base + 2678656); + output_41->quant_channel = 1; + struct csinn_relu_params *params_41 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_41->base.name = "relu_relu5_4/sep_83"; + csinn_relu_init(output_40, output_41, params_41); + struct csinn_tensor *output_42 = csinn_alloc_tensor(sess); + output_42->name = "output_42"; + output_42->dtype = CSINN_DTYPE_FLOAT16; + output_42->layout = CSINN_LAYOUT_NCHW; + output_42->dim[0] = 1; + output_42->dim[1] = 512; + output_42->dim[2] = 14; + output_42->dim[3] = 14; + output_42->dim_count = 4; + output_42->qinfo = (struct csinn_quant_info *)(params_base + 2678680); + output_42->quant_channel = 1; + struct csinn_tensor *kernel_42 = csinn_alloc_tensor(sess); + kernel_42->name = "kernel_42"; + kernel_42->data = params_base + 2678728; + kernel_42->is_const = 1; + kernel_42->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_42->dtype = CSINN_DTYPE_FLOAT16; + kernel_42->layout = CSINN_LAYOUT_O1HW; + kernel_42->dim[0] = 512; + kernel_42->dim[1] = 1; + kernel_42->dim[2] = 3; + kernel_42->dim[3] = 3; + kernel_42->dim_count = 4; + kernel_42->qinfo = (struct csinn_quant_info *)(params_base + 2678704); + kernel_42->quant_channel = 1; + struct csinn_tensor *bias_42 = csinn_alloc_tensor(sess); + bias_42->name = "bias_42"; + bias_42->data = params_base + 2688000; + bias_42->is_const = 1; + bias_42->dtype = CSINN_DTYPE_FLOAT16; + bias_42->layout = CSINN_LAYOUT_O; + bias_42->dim[0] = 512; + bias_42->dim_count = 1; + bias_42->qinfo = (struct csinn_quant_info *)(params_base + 2687976); + bias_42->quant_channel = 1; + struct csinn_conv2d_params *params_42 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_42->group = 512; + params_42->stride_height = 1; + params_42->stride_width = 1; + params_42->dilation_height = 1; + params_42->dilation_width = 1; + params_42->conv_extra.kernel_tm = NULL; + params_42->conv_extra.conv_mode = CSINN_DIRECT; + params_42->pad_top = 1; + params_42->pad_left = 1; + params_42->pad_down = 1; + params_42->pad_right = 1; + params_42->base.name = "conv2d_conv5_5/dw_84_fuse_multiply_85_fuse_add_conv5_5/dw/bn_PART_0_86"; + csinn_conv2d_init(output_41, output_42, kernel_42, bias_42, params_42); + struct csinn_tensor *output_43 = csinn_alloc_tensor(sess); + output_43->name = "output_43"; + output_43->dtype = CSINN_DTYPE_FLOAT16; + output_43->layout = CSINN_LAYOUT_NCHW; + output_43->dim[0] = 1; + output_43->dim[1] = 512; + output_43->dim[2] = 14; + output_43->dim[3] = 14; + output_43->dim_count = 4; + output_43->qinfo = (struct csinn_quant_info *)(params_base + 2689024); + output_43->quant_channel = 1; + struct csinn_relu_params *params_43 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_43->base.name = "relu_relu5_5/dw_87"; + csinn_relu_init(output_42, output_43, params_43); + struct csinn_tensor *output_44 = csinn_alloc_tensor(sess); + output_44->name = "output_44"; + output_44->dtype = CSINN_DTYPE_FLOAT16; + output_44->layout = CSINN_LAYOUT_NCHW; + output_44->dim[0] = 1; + output_44->dim[1] = 512; + output_44->dim[2] = 14; + output_44->dim[3] = 14; + output_44->dim_count = 4; + output_44->qinfo = (struct csinn_quant_info *)(params_base + 2689048); + output_44->quant_channel = 1; + struct csinn_tensor *kernel_44 = csinn_alloc_tensor(sess); + kernel_44->name = "kernel_44"; + kernel_44->data = params_base + 2689096; + kernel_44->is_const = 1; + kernel_44->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_44->dtype = CSINN_DTYPE_FLOAT16; + kernel_44->layout = CSINN_LAYOUT_OIHW; + kernel_44->dim[0] = 512; + kernel_44->dim[1] = 512; + kernel_44->dim[2] = 1; + kernel_44->dim[3] = 1; + kernel_44->dim_count = 4; + kernel_44->qinfo = (struct csinn_quant_info *)(params_base + 2689072); + kernel_44->quant_channel = 1; + struct csinn_tensor *bias_44 = csinn_alloc_tensor(sess); + bias_44->name = "bias_44"; + bias_44->data = params_base + 3213440; + bias_44->is_const = 1; + bias_44->dtype = CSINN_DTYPE_FLOAT16; + bias_44->layout = CSINN_LAYOUT_O; + bias_44->dim[0] = 512; + bias_44->dim_count = 1; + bias_44->qinfo = (struct csinn_quant_info *)(params_base + 3213416); + bias_44->quant_channel = 1; + struct csinn_conv2d_params *params_44 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_44->group = 1; + params_44->stride_height = 1; + params_44->stride_width = 1; + params_44->dilation_height = 1; + params_44->dilation_width = 1; + params_44->conv_extra.kernel_tm = NULL; + params_44->conv_extra.conv_mode = CSINN_DIRECT; + params_44->pad_top = 0; + params_44->pad_left = 0; + params_44->pad_down = 0; + params_44->pad_right = 0; + params_44->base.name = + "conv2d_conv5_5/sep_88_fuse_multiply_89_fuse_add_conv5_5/sep/bn_PART_0_90"; + csinn_conv2d_init(output_43, output_44, kernel_44, bias_44, params_44); + struct csinn_tensor *output_45 = csinn_alloc_tensor(sess); + output_45->name = "output_45"; + output_45->dtype = CSINN_DTYPE_FLOAT16; + output_45->layout = CSINN_LAYOUT_NCHW; + output_45->dim[0] = 1; + output_45->dim[1] = 512; + output_45->dim[2] = 14; + output_45->dim[3] = 14; + output_45->dim_count = 4; + output_45->qinfo = (struct csinn_quant_info *)(params_base + 3214464); + output_45->quant_channel = 1; + struct csinn_relu_params *params_45 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_45->base.name = "relu_relu5_5/sep_91"; + csinn_relu_init(output_44, output_45, params_45); + struct csinn_tensor *output_46 = csinn_alloc_tensor(sess); + output_46->name = "output_46"; + output_46->dtype = CSINN_DTYPE_FLOAT16; + output_46->layout = CSINN_LAYOUT_NCHW; + output_46->dim[0] = 1; + output_46->dim[1] = 512; + output_46->dim[2] = 7; + output_46->dim[3] = 7; + output_46->dim_count = 4; + output_46->qinfo = (struct csinn_quant_info *)(params_base + 3214488); + output_46->quant_channel = 1; + struct csinn_tensor *kernel_46 = csinn_alloc_tensor(sess); + kernel_46->name = "kernel_46"; + kernel_46->data = params_base + 3214536; + kernel_46->is_const = 1; + kernel_46->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_46->dtype = CSINN_DTYPE_FLOAT16; + kernel_46->layout = CSINN_LAYOUT_O1HW; + kernel_46->dim[0] = 512; + kernel_46->dim[1] = 1; + kernel_46->dim[2] = 3; + kernel_46->dim[3] = 3; + kernel_46->dim_count = 4; + kernel_46->qinfo = (struct csinn_quant_info *)(params_base + 3214512); + kernel_46->quant_channel = 1; + struct csinn_tensor *bias_46 = csinn_alloc_tensor(sess); + bias_46->name = "bias_46"; + bias_46->data = params_base + 3223808; + bias_46->is_const = 1; + bias_46->dtype = CSINN_DTYPE_FLOAT16; + bias_46->layout = CSINN_LAYOUT_O; + bias_46->dim[0] = 512; + bias_46->dim_count = 1; + bias_46->qinfo = (struct csinn_quant_info *)(params_base + 3223784); + bias_46->quant_channel = 1; + struct csinn_conv2d_params *params_46 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_46->group = 512; + params_46->stride_height = 2; + params_46->stride_width = 2; + params_46->dilation_height = 1; + params_46->dilation_width = 1; + params_46->conv_extra.kernel_tm = NULL; + params_46->conv_extra.conv_mode = CSINN_DIRECT; + params_46->pad_top = 1; + params_46->pad_left = 1; + params_46->pad_down = 1; + params_46->pad_right = 1; + params_46->base.name = "conv2d_conv5_6/dw_92_fuse_multiply_93_fuse_add_conv5_6/dw/bn_PART_0_94"; + csinn_conv2d_init(output_45, output_46, kernel_46, bias_46, params_46); + struct csinn_tensor *output_47 = csinn_alloc_tensor(sess); + output_47->name = "output_47"; + output_47->dtype = CSINN_DTYPE_FLOAT16; + output_47->layout = CSINN_LAYOUT_NCHW; + output_47->dim[0] = 1; + output_47->dim[1] = 512; + output_47->dim[2] = 7; + output_47->dim[3] = 7; + output_47->dim_count = 4; + output_47->qinfo = (struct csinn_quant_info *)(params_base + 3224832); + output_47->quant_channel = 1; + struct csinn_relu_params *params_47 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_47->base.name = "relu_relu5_6/dw_95"; + csinn_relu_init(output_46, output_47, params_47); + struct csinn_tensor *output_48 = csinn_alloc_tensor(sess); + output_48->name = "output_48"; + output_48->dtype = CSINN_DTYPE_FLOAT16; + output_48->layout = CSINN_LAYOUT_NCHW; + output_48->dim[0] = 1; + output_48->dim[1] = 1024; + output_48->dim[2] = 7; + output_48->dim[3] = 7; + output_48->dim_count = 4; + output_48->qinfo = (struct csinn_quant_info *)(params_base + 3224856); + output_48->quant_channel = 1; + struct csinn_tensor *kernel_48 = csinn_alloc_tensor(sess); + kernel_48->name = "kernel_48"; + kernel_48->data = params_base + 3224904; + kernel_48->is_const = 1; + kernel_48->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_48->dtype = CSINN_DTYPE_FLOAT16; + kernel_48->layout = CSINN_LAYOUT_OIHW; + kernel_48->dim[0] = 1024; + kernel_48->dim[1] = 512; + kernel_48->dim[2] = 1; + kernel_48->dim[3] = 1; + kernel_48->dim_count = 4; + kernel_48->qinfo = (struct csinn_quant_info *)(params_base + 3224880); + kernel_48->quant_channel = 1; + struct csinn_tensor *bias_48 = csinn_alloc_tensor(sess); + bias_48->name = "bias_48"; + bias_48->data = params_base + 4273536; + bias_48->is_const = 1; + bias_48->dtype = CSINN_DTYPE_FLOAT16; + bias_48->layout = CSINN_LAYOUT_O; + bias_48->dim[0] = 1024; + bias_48->dim_count = 1; + bias_48->qinfo = (struct csinn_quant_info *)(params_base + 4273512); + bias_48->quant_channel = 1; + struct csinn_conv2d_params *params_48 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_48->group = 1; + params_48->stride_height = 1; + params_48->stride_width = 1; + params_48->dilation_height = 1; + params_48->dilation_width = 1; + params_48->conv_extra.kernel_tm = NULL; + params_48->conv_extra.conv_mode = CSINN_DIRECT; + params_48->pad_top = 0; + params_48->pad_left = 0; + params_48->pad_down = 0; + params_48->pad_right = 0; + params_48->base.name = + "conv2d_conv5_6/sep_96_fuse_multiply_97_fuse_add_conv5_6/sep/bn_PART_0_98"; + csinn_conv2d_init(output_47, output_48, kernel_48, bias_48, params_48); + struct csinn_tensor *output_49 = csinn_alloc_tensor(sess); + output_49->name = "output_49"; + output_49->dtype = CSINN_DTYPE_FLOAT16; + output_49->layout = CSINN_LAYOUT_NCHW; + output_49->dim[0] = 1; + output_49->dim[1] = 1024; + output_49->dim[2] = 7; + output_49->dim[3] = 7; + output_49->dim_count = 4; + output_49->qinfo = (struct csinn_quant_info *)(params_base + 4275584); + output_49->quant_channel = 1; + struct csinn_relu_params *params_49 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_49->base.name = "relu_relu5_6/sep_99"; + csinn_relu_init(output_48, output_49, params_49); + struct csinn_tensor *output_50 = csinn_alloc_tensor(sess); + output_50->name = "output_50"; + output_50->dtype = CSINN_DTYPE_FLOAT16; + output_50->layout = CSINN_LAYOUT_NCHW; + output_50->dim[0] = 1; + output_50->dim[1] = 1024; + output_50->dim[2] = 7; + output_50->dim[3] = 7; + output_50->dim_count = 4; + output_50->qinfo = (struct csinn_quant_info *)(params_base + 4275608); + output_50->quant_channel = 1; + struct csinn_tensor *kernel_50 = csinn_alloc_tensor(sess); + kernel_50->name = "kernel_50"; + kernel_50->data = params_base + 4275656; + kernel_50->is_const = 1; + kernel_50->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_50->dtype = CSINN_DTYPE_FLOAT16; + kernel_50->layout = CSINN_LAYOUT_O1HW; + kernel_50->dim[0] = 1024; + kernel_50->dim[1] = 1; + kernel_50->dim[2] = 3; + kernel_50->dim[3] = 3; + kernel_50->dim_count = 4; + kernel_50->qinfo = (struct csinn_quant_info *)(params_base + 4275632); + kernel_50->quant_channel = 1; + struct csinn_tensor *bias_50 = csinn_alloc_tensor(sess); + bias_50->name = "bias_50"; + bias_50->data = params_base + 4294144; + bias_50->is_const = 1; + bias_50->dtype = CSINN_DTYPE_FLOAT16; + bias_50->layout = CSINN_LAYOUT_O; + bias_50->dim[0] = 1024; + bias_50->dim_count = 1; + bias_50->qinfo = (struct csinn_quant_info *)(params_base + 4294120); + bias_50->quant_channel = 1; + struct csinn_conv2d_params *params_50 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_50->group = 1024; + params_50->stride_height = 1; + params_50->stride_width = 1; + params_50->dilation_height = 1; + params_50->dilation_width = 1; + params_50->conv_extra.kernel_tm = NULL; + params_50->conv_extra.conv_mode = CSINN_DIRECT; + params_50->pad_top = 1; + params_50->pad_left = 1; + params_50->pad_down = 1; + params_50->pad_right = 1; + params_50->base.name = "conv2d_conv6/dw_100_fuse_multiply_101_fuse_add_conv6/dw/bn_PART_0_102"; + csinn_conv2d_init(output_49, output_50, kernel_50, bias_50, params_50); + struct csinn_tensor *output_51 = csinn_alloc_tensor(sess); + output_51->name = "output_51"; + output_51->dtype = CSINN_DTYPE_FLOAT16; + output_51->layout = CSINN_LAYOUT_NCHW; + output_51->dim[0] = 1; + output_51->dim[1] = 1024; + output_51->dim[2] = 7; + output_51->dim[3] = 7; + output_51->dim_count = 4; + output_51->qinfo = (struct csinn_quant_info *)(params_base + 4296192); + output_51->quant_channel = 1; + struct csinn_relu_params *params_51 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_51->base.name = "relu_relu6/dw_103"; + csinn_relu_init(output_50, output_51, params_51); + struct csinn_tensor *output_52 = csinn_alloc_tensor(sess); + output_52->name = "output_52"; + output_52->dtype = CSINN_DTYPE_FLOAT16; + output_52->layout = CSINN_LAYOUT_NCHW; + output_52->dim[0] = 1; + output_52->dim[1] = 1024; + output_52->dim[2] = 7; + output_52->dim[3] = 7; + output_52->dim_count = 4; + output_52->qinfo = (struct csinn_quant_info *)(params_base + 4296216); + output_52->quant_channel = 1; + struct csinn_tensor *kernel_52 = csinn_alloc_tensor(sess); + kernel_52->name = "kernel_52"; + kernel_52->data = params_base + 4296264; + kernel_52->is_const = 1; + kernel_52->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_52->dtype = CSINN_DTYPE_FLOAT16; + kernel_52->layout = CSINN_LAYOUT_OIHW; + kernel_52->dim[0] = 1024; + kernel_52->dim[1] = 1024; + kernel_52->dim[2] = 1; + kernel_52->dim[3] = 1; + kernel_52->dim_count = 4; + kernel_52->qinfo = (struct csinn_quant_info *)(params_base + 4296240); + kernel_52->quant_channel = 1; + struct csinn_tensor *bias_52 = csinn_alloc_tensor(sess); + bias_52->name = "bias_52"; + bias_52->data = params_base + 6393472; + bias_52->is_const = 1; + bias_52->dtype = CSINN_DTYPE_FLOAT16; + bias_52->layout = CSINN_LAYOUT_O; + bias_52->dim[0] = 1024; + bias_52->dim_count = 1; + bias_52->qinfo = (struct csinn_quant_info *)(params_base + 6393448); + bias_52->quant_channel = 1; + struct csinn_conv2d_params *params_52 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_52->group = 1; + params_52->stride_height = 1; + params_52->stride_width = 1; + params_52->dilation_height = 1; + params_52->dilation_width = 1; + params_52->conv_extra.kernel_tm = NULL; + params_52->conv_extra.conv_mode = CSINN_DIRECT; + params_52->pad_top = 0; + params_52->pad_left = 0; + params_52->pad_down = 0; + params_52->pad_right = 0; + params_52->base.name = + "conv2d_conv6/sep_104_fuse_multiply_105_fuse_add_conv6/sep/bn_PART_0_106"; + csinn_conv2d_init(output_51, output_52, kernel_52, bias_52, params_52); + struct csinn_tensor *output_53 = csinn_alloc_tensor(sess); + output_53->name = "output_53"; + output_53->dtype = CSINN_DTYPE_FLOAT16; + output_53->layout = CSINN_LAYOUT_NCHW; + output_53->dim[0] = 1; + output_53->dim[1] = 1024; + output_53->dim[2] = 7; + output_53->dim[3] = 7; + output_53->dim_count = 4; + output_53->qinfo = (struct csinn_quant_info *)(params_base + 6395520); + output_53->quant_channel = 1; + struct csinn_relu_params *params_53 = + csinn_alloc_params(sizeof(struct csinn_relu_params), sess); + params_53->base.name = "relu_relu6/sep_107"; + csinn_relu_init(output_52, output_53, params_53); + struct csinn_tensor *output_54 = csinn_alloc_tensor(sess); + output_54->name = "output_54"; + output_54->dtype = CSINN_DTYPE_FLOAT16; + output_54->layout = CSINN_LAYOUT_NCHW; + output_54->dim[0] = 1; + output_54->dim[1] = 1024; + output_54->dim[2] = 1; + output_54->dim[3] = 1; + output_54->dim_count = 4; + output_54->qinfo = (struct csinn_quant_info *)(params_base + 6395544); + output_54->quant_channel = 1; + struct csinn_pool_params *params_54 = + csinn_alloc_params(sizeof(struct csinn_pool_params), sess); + params_54->base.name = "global_avg_pool2d_pool6_108"; + csinn_global_avgpool2d_init(output_53, output_54, params_54); + struct csinn_tensor *output_55 = csinn_alloc_tensor(sess); + output_55->name = "output_55"; + output_55->dtype = CSINN_DTYPE_FLOAT16; + output_55->layout = CSINN_LAYOUT_NCHW; + output_55->dim[0] = 1; + output_55->dim[1] = 1000; + output_55->dim[2] = 1; + output_55->dim[3] = 1; + output_55->dim_count = 4; + output_55->qinfo = (struct csinn_quant_info *)(params_base + 6395568); + output_55->quant_channel = 1; + struct csinn_tensor *kernel_55 = csinn_alloc_tensor(sess); + kernel_55->name = "kernel_55"; + kernel_55->data = params_base + 6395616; + kernel_55->is_const = 1; + kernel_55->mtype = CSINN_MEM_TYPE_CPU_ALIGNED; + kernel_55->dtype = CSINN_DTYPE_FLOAT16; + kernel_55->layout = CSINN_LAYOUT_OIHW; + kernel_55->dim[0] = 1000; + kernel_55->dim[1] = 1024; + kernel_55->dim[2] = 1; + kernel_55->dim[3] = 1; + kernel_55->dim_count = 4; + kernel_55->qinfo = (struct csinn_quant_info *)(params_base + 6395592); + kernel_55->quant_channel = 1; + struct csinn_tensor *bias_55 = csinn_alloc_tensor(sess); + bias_55->name = "bias_55"; + bias_55->data = params_base + 8443672; + bias_55->is_const = 1; + bias_55->dtype = CSINN_DTYPE_FLOAT16; + bias_55->layout = CSINN_LAYOUT_O; + bias_55->dim[0] = 1000; + bias_55->dim_count = 1; + bias_55->qinfo = (struct csinn_quant_info *)(params_base + 8443648); + bias_55->quant_channel = 1; + struct csinn_conv2d_params *params_55 = + csinn_alloc_params(sizeof(struct csinn_conv2d_params), sess); + params_55->group = 1; + params_55->stride_height = 1; + params_55->stride_width = 1; + params_55->dilation_height = 1; + params_55->dilation_width = 1; + params_55->conv_extra.kernel_tm = NULL; + params_55->conv_extra.conv_mode = CSINN_DIRECT; + params_55->pad_top = 0; + params_55->pad_left = 0; + params_55->pad_down = 0; + params_55->pad_right = 0; + params_55->base.name = "conv2d_fc7_PART_0_109_fuse_bias_add_fc7_110"; + csinn_conv2d_init(output_54, output_55, kernel_55, bias_55, params_55); + struct csinn_tensor *output_56 = csinn_alloc_tensor(sess); + output_56->name = "softmax_output@@prob_111_56"; + output_56->dtype = CSINN_DTYPE_FLOAT16; + output_56->layout = CSINN_LAYOUT_NCHW; + output_56->dim[0] = 1; + output_56->dim[1] = 1000; + output_56->dim[2] = 1; + output_56->dim[3] = 1; + output_56->dim_count = 4; + output_56->qinfo = (struct csinn_quant_info *)(params_base + 8445672); + output_56->quant_channel = 1; + struct csinn_softmax_params *params_56 = + csinn_alloc_params(sizeof(struct csinn_softmax_params), sess); + params_56->axis = 1; + params_56->base.name = "softmax_output@@prob_111"; + csinn_softmax_init(output_55, output_56, params_56); + csinn_set_tensor_entry(data, sess); + csinn_set_input(0, data, sess); + + csinn_conv2d(data, output_0, kernel_0, bias_0, params_0); + csinn_relu(output_0, output_1, params_1); + csinn_conv2d(output_1, output_2, kernel_2, bias_2, params_2); + csinn_relu(output_2, output_3, params_3); + csinn_conv2d(output_3, output_4, kernel_4, bias_4, params_4); + csinn_relu(output_4, output_5, params_5); + csinn_conv2d(output_5, output_6, kernel_6, bias_6, params_6); + csinn_relu(output_6, output_7, params_7); + csinn_conv2d(output_7, output_8, kernel_8, bias_8, params_8); + csinn_relu(output_8, output_9, params_9); + csinn_conv2d(output_9, output_10, kernel_10, bias_10, params_10); + csinn_relu(output_10, output_11, params_11); + csinn_conv2d(output_11, output_12, kernel_12, bias_12, params_12); + csinn_relu(output_12, output_13, params_13); + csinn_conv2d(output_13, output_14, kernel_14, bias_14, params_14); + csinn_relu(output_14, output_15, params_15); + csinn_conv2d(output_15, output_16, kernel_16, bias_16, params_16); + csinn_relu(output_16, output_17, params_17); + csinn_conv2d(output_17, output_18, kernel_18, bias_18, params_18); + csinn_relu(output_18, output_19, params_19); + csinn_conv2d(output_19, output_20, kernel_20, bias_20, params_20); + csinn_relu(output_20, output_21, params_21); + csinn_conv2d(output_21, output_22, kernel_22, bias_22, params_22); + csinn_relu(output_22, output_23, params_23); + csinn_conv2d(output_23, output_24, kernel_24, bias_24, params_24); + csinn_relu(output_24, output_25, params_25); + csinn_conv2d(output_25, output_26, kernel_26, bias_26, params_26); + csinn_relu(output_26, output_27, params_27); + csinn_conv2d(output_27, output_28, kernel_28, bias_28, params_28); + csinn_relu(output_28, output_29, params_29); + csinn_conv2d(output_29, output_30, kernel_30, bias_30, params_30); + csinn_relu(output_30, output_31, params_31); + csinn_conv2d(output_31, output_32, kernel_32, bias_32, params_32); + csinn_relu(output_32, output_33, params_33); + csinn_conv2d(output_33, output_34, kernel_34, bias_34, params_34); + csinn_relu(output_34, output_35, params_35); + csinn_conv2d(output_35, output_36, kernel_36, bias_36, params_36); + csinn_relu(output_36, output_37, params_37); + csinn_conv2d(output_37, output_38, kernel_38, bias_38, params_38); + csinn_relu(output_38, output_39, params_39); + csinn_conv2d(output_39, output_40, kernel_40, bias_40, params_40); + csinn_relu(output_40, output_41, params_41); + csinn_conv2d(output_41, output_42, kernel_42, bias_42, params_42); + csinn_relu(output_42, output_43, params_43); + csinn_conv2d(output_43, output_44, kernel_44, bias_44, params_44); + csinn_relu(output_44, output_45, params_45); + csinn_conv2d(output_45, output_46, kernel_46, bias_46, params_46); + csinn_relu(output_46, output_47, params_47); + csinn_conv2d(output_47, output_48, kernel_48, bias_48, params_48); + csinn_relu(output_48, output_49, params_49); + csinn_conv2d(output_49, output_50, kernel_50, bias_50, params_50); + csinn_relu(output_50, output_51, params_51); + csinn_conv2d(output_51, output_52, kernel_52, bias_52, params_52); + csinn_relu(output_52, output_53, params_53); + csinn_global_avgpool2d(output_53, output_54, params_54); + csinn_conv2d(output_54, output_55, kernel_55, bias_55, params_55); + csinn_softmax(output_55, output_56, params_56); + csinn_set_output(0, output_56, sess); + + csinn_session_setup(sess); + return sess; +} +void csinn_run(void *data0, void *sess) +{ + struct csinn_tensor input_tensor; + input_tensor.data = data0; + csinn_update_input(0, &input_tensor, sess); + csinn_session_run(sess); +} + +int main(int argc, char **argv) +{ + /* alloc random params */ + void *params = malloc(8453888); + void *sess = csinn_(params + 8192); + + /* alloc random input */ + void *input = malloc(224 * 224 * 3 * 2); + uint64_t start_time, end_time; + + start_time = shl_get_timespec(); + csinn_run(input, sess); + end_time = shl_get_timespec(); + printf("Run graph execution time: %.5fms, FPS=%.2f\n", + ((float)(end_time - start_time)) / 1000000, + 1000000000.0 / ((float)(end_time - start_time))); + + csinn_session_deinit(sess); + csinn_free_session(sess); + free(params); + free(input); + + return 0; +}