remove vitis platform dependencies on external repo (#48)

Co-authored-by: Rock Qu <yunq@xilinx.com>

boards/Makefile

@@ -43,7 +43,11 @@ check_env :
 
 ${VITIS_PLATFORM} :
 	@echo "Preparing Vitis platform for ${BOARD}..."
-	bash get_platform.sh ${BOARD} ${VITIS_PLATFORM}
+	cd vitis_platform/dpu && make clean && make BOARD=${BOARD}
+	cd vitis_platform && make XSA_PATH=./dpu/dpu.xsa BOARD=${BOARD}
+	cp -rf vitis_platform/${BOARD}/platforms/dpu ${BOARD}
+	@echo "Successfully finished building vitis platform."
+	@echo "Vitis platform stored in $(BOARD)/dpu."
 
 XOCC_OPTS = -t ${TARGET} --platform ${VITIS_PLATFORM} \
 	--save-temps --config ${DIR_PRJ}/prj_config \

boards/vitis_platform/Makefile

@@ -0,0 +1,59 @@
+XSA_PATH := ../ultra/ultra.xsa
+BOARD := ZCU104
+
+OVERLAY := $(shell basename $(XSA_PATH) | cut -d "." -f 1)
+
+Zynq7000 := 
+ZynqUltrascale := Ultra96 ZCU104 ZCU111
+ifneq ($(filter $(BOARD),$(Zynq7000)),)
+PROC = ps7_cortexa9
+endif
+ifneq ($(filter $(BOARD),$(ZynqUltrascale)),)
+PROC = psu_cortexa53
+endif
+ifndef PROC
+$(error Please set BOARD to one of the supported boards)
+endif
+
+all: clean help $(BOARD)/platforms/$(OVERLAY)/$(OVERLAY).xpfm
+
+.PHONY: clean cleanall help
+
+help:
+	@echo "usage: make [target]"
+	@echo
+	@echo "options:"
+	@echo "--------"
+	@echo "all:        clean, show help message, and make the platform."
+	@echo "help:       show help message."
+	@echo "platform:   make the Vitis platform."
+	@echo "clean:      clean Vitis platform for a given overlay."
+	@echo
+	@echo "arguments:"
+	@echo "----------"
+	@echo "XSA_PATH:   path to the xsa file"
+	@echo "            e.g., /home/usr/boards/ZCU104/ultra/ultra.xsa"
+	@echo "BOARD:      name of the board"
+	@echo "            e.g., ZCU104, Ultra96, ZCU111"
+	@echo
+	@echo "current configuration:"
+	@echo "----------------------"
+	@echo "make XSA_PATH=$(XSA_PATH)"
+	@echo "     BOARD=$(BOARD)"
+	@echo
+
+$(BOARD)/platforms/$(OVERLAY)/$(OVERLAY).xpfm:
+	mkdir -p ./$(BOARD)/platforms
+	xsct -sdx build_pfm.tcl $(XSA_PATH) $(OVERLAY) $(BOARD) $(PROC)
+	rm -rf ./$(BOARD)/platforms/$(OVERLAY)
+	cp -rf ./$(BOARD)/output/$(OVERLAY)/export/$(OVERLAY) \
+	$(BOARD)/platforms/$(OVERLAY)
+	@echo "Successfully finished building vitis platform."
+	@echo "Vitis platform stored in $(BOARD)/platforms/$(OVERLAY)."
+
+clean:
+	rm -rf ./*/output
+
+cleanall: clean
+	rm -rf ./*/platforms
+

boards/vitis_platform/Ultra96/src/a53/xrt/linux.bif

@@ -0,0 +1,6 @@
+/* linux */
+the_ROM_image:
+{
+
+}
+

boards/vitis_platform/Ultra96/src/generic.readme

@@ -0,0 +1,23 @@
+-= SD card boot image =-
+
+Platform: <platform>
+Application: <elf>
+
+Note all the binaries in this platform are dummy files. As a result,
+users won't be able to use the boot parition generated by our flow.
+Our flow introduced in this repo is a very special use case, where
+we only use the Vitis platform to generate the hardware design.
+We rely on the PYNQ boot sequence and load bitstream after boot into Linux.
+
+To generate the real boot partition, users will have to manually replace
+the following files:
+
+1. image.ub
+2. bl31.elf
+3. fsbl.elf
+4. pmufw.elf
+5. u-boot.elf
+
+These files usually can be found after running the PYNQ sdbuild flow. If 
+users use the real binary files, the boot parition generated using Vitis
+will be a valid boot partition.

boards/vitis_platform/ZCU104/src/a53/xrt/linux.bif

@@ -0,0 +1,6 @@
+/* linux */
+the_ROM_image:
+{
+
+}
+

boards/vitis_platform/ZCU104/src/generic.readme

@@ -0,0 +1,23 @@
+-= SD card boot image =-
+
+Platform: <platform>
+Application: <elf>
+
+Note all the binaries in this platform are dummy files. As a result,
+users won't be able to use the boot parition generated by our flow.
+Our flow introduced in this repo is a very special use case, where
+we only use the Vitis platform to generate the hardware design.
+We rely on the PYNQ boot sequence and load bitstream after boot into Linux.
+
+To generate the real boot partition, users will have to manually replace
+the following files:
+
+1. image.ub
+2. bl31.elf
+3. fsbl.elf
+4. pmufw.elf
+5. u-boot.elf
+
+These files usually can be found after running the PYNQ sdbuild flow. If 
+users use the real binary files, the boot parition generated using Vitis
+will be a valid boot partition.

boards/vitis_platform/ZCU111/src/a53/xrt/linux.bif

@@ -0,0 +1,6 @@
+/* linux */
+the_ROM_image:
+{
+
+}
+

boards/vitis_platform/ZCU111/src/generic.readme

@@ -0,0 +1,23 @@
+-= SD card boot image =-
+
+Platform: <platform>
+Application: <elf>
+
+Note all the binaries in this platform are dummy files. As a result,
+users won't be able to use the boot parition generated by our flow.
+Our flow introduced in this repo is a very special use case, where
+we only use the Vitis platform to generate the hardware design.
+We rely on the PYNQ boot sequence and load bitstream after boot into Linux.
+
+To generate the real boot partition, users will have to manually replace
+the following files:
+
+1. image.ub
+2. bl31.elf
+3. fsbl.elf
+4. pmufw.elf
+5. u-boot.elf
+
+These files usually can be found after running the PYNQ sdbuild flow. If 
+users use the real binary files, the boot parition generated using Vitis
+will be a valid boot partition.

boards/vitis_platform/build_pfm.tcl

@@ -0,0 +1,24 @@
+set xsa_path [lindex $argv 0]
+set overlay_name [lindex $argv 1]
+set board [lindex $argv 2]
+set processor [lindex $argv 3]
+
+if { ${processor} eq "psu_cortexa53" } {
+	set ps a53
+} elseif { ${processor} eq "ps7_cortexa9" } {
+	set ps a9
+} else {
+	puts "Wrong processor name provided."
+	exit 1
+}
+
+platform -name ${overlay_name} -desc "A vitis platform for ${board}" \
+	-hw ${xsa_path} -out ./${board}/output -prebuilt
+
+domain -name xrt -proc ${processor} -os linux \
+	-image ./${board}/src/${ps}/xrt/image
+domain config -boot ./${board}/src/boot
+domain config -bif ./${board}/src/${ps}/xrt/linux.bif
+domain -runtime opencl
+
+platform -generate

boards/vitis_platform/dpu/Makefile

@@ -0,0 +1,37 @@
+overlay_name := dpu
+
+BOARD=Ultra96
+ifeq ($(BOARD),Ultra96)
+	device=xczu3eg-sbva484-1-i
+endif
+ifeq ($(BOARD),ZCU104)
+	device=xczu7ev-ffvc1156-2-e
+endif
+ifeq ($(BOARD),ZCU111)
+	device=xczu28dr-ffvg1517-2-e
+endif
+ifndef device
+$(error Please set BOARD to one of the supported boards)
+endif
+
+all: block_design bitstream check_timing
+	@echo
+	@tput setaf 2 ; echo "Built $(overlay_name) successfully!"; tput sgr0;
+	@echo
+
+block_design:
+	@sed -i "s/\(create_project \)\(.*\)\( -part \)\(.*\)"\
+	"/\1$(overlay_name) $(overlay_name)\3$(device)/" \
+	$(overlay_name).tcl; \
+	sed -i 's/^set design_name \(.*\)/set design_name $(overlay_name)/g' \
+	$(overlay_name).tcl; \
+	vivado -mode batch -source $(overlay_name).tcl -notrace
+
+bitstream:
+	vivado -mode batch -source build_bitstream.tcl -notrace
+
+check_timing:
+	vivado -mode batch -source check_timing.tcl -notrace
+
+clean:
+	rm -rf $(overlay_name) *.jou *.log NA

boards/vitis_platform/dpu/build_bitstream.tcl

@@ -0,0 +1,32 @@
+set overlay_name "dpu"
+
+# open block design
+open_project ./${overlay_name}/${overlay_name}.xpr
+open_bd_design ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${overlay_name}/${overlay_name}.bd
+
+# add top wrapper
+make_wrapper -files [get_files ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${overlay_name}/${overlay_name}.bd] -top
+add_files -norecurse ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${overlay_name}/hdl/${overlay_name}_wrapper.v
+set_property top ${overlay_name}_wrapper [current_fileset]
+update_compile_order -fileset sources_1
+
+# set platform properties
+set_property platform.default_output_type "sd_card" [current_project]
+set_property platform.design_intent.embedded "true" [current_project]
+set_property platform.design_intent.server_managed "false" [current_project]
+set_property platform.design_intent.external_host "false" [current_project]
+set_property platform.design_intent.datacenter "false" [current_project]
+
+# call implement
+launch_runs impl_1 -to_step write_bitstream -jobs 4
+wait_on_run impl_1
+
+# generate xsa
+write_hw_platform -force ./${overlay_name}.xsa
+validate_hw_platform ./${overlay_name}.xsa
+
+# move and rename bitstream to final location
+file copy -force ./${overlay_name}/${overlay_name}.runs/impl_1/${overlay_name}_wrapper.bit ${overlay_name}.bit
+
+# copy hwh files
+file copy -force ./${overlay_name}/${overlay_name}.gen/sources_1/bd/${overlay_name}/hw_handoff/${overlay_name}.hwh ${overlay_name}.hwh

boards/vitis_platform/dpu/check_timing.tcl

@@ -0,0 +1,15 @@
+set overlay_name "dpu"
+
+set fd [open ./${overlay_name}/${overlay_name}.runs/impl_1/${overlay_name}_wrapper_timing_summary_routed.rpt r]
+set timing_met 0
+while { [gets $fd line] >= 0 } {
+    if [string match {All user specified timing constraints are met.} $line]  { 
+        set timing_met 1
+        break
+    }
+}
+if {$timing_met == 0} {
+    puts "ERROR: ${overlay_name} bitstream generation does not meet timing."
+    exit 1
+}
+puts "Timing constraints are met."