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4bitRCA180nm
4bitRCA180nm PublicPerformance Analysis of a 4-bit Ripple Carry Adder (RCA) formed using Static CMOS, Transmission Gate, NMOS Pass Transistor Logic at gpdk 180nm Technology node.
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Chess-Clock
Chess-Clock PublicA two player digital chess clock controller used to keep track of time in hrs:mins:sec taken by each player while making their respective move during the passage of the game.
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32-bit-Signed-Vedic-Multiplier
32-bit-Signed-Vedic-Multiplier PublicA 32-bit Signed Vedic Multiplier created using Verilog HDL utilising Vedic Mathematic Sutras formed using Carry Lookahead Adders as the basic building blocks.
Verilog 1
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Hardware-Security-on-Memories
Hardware-Security-on-Memories PublicThis project is an attempt to develop hardware solutions to enhance the security of semiconductor memories. As part of this, we implement an Analog Hardware Trojan (a type of hardware attack) to st…
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Oven-FSM-RTL-to-GDS-II-design-using-Qflow
Oven-FSM-RTL-to-GDS-II-design-using-Qflow PublicRTL to GDS II flow for a custom "Oven FSM" ASIC design utilising Qflow, an Open Source Physical Design toolchain.
Verilog 1
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BIST-for-6bit-CLA
BIST-for-6bit-CLA PublicA Built in Self Test (BIST) controller is created in Verilog HDL to test a 6-bit Carry Lookahead Adder (CLA) utilising a 4-bit Signature Output Response Analyser (ORA).
Verilog 1
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