Release version 0.32

CHANGELOG

@@ -2,8 +2,15 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.31 .. Yosys 0.32-dev
+Yosys 0.31 .. Yosys 0.32
 --------------------------
+ * Verific support
+    - Added sub option "-lib" to reading commands for VHDL and
+      SystemVerilog, that will later import all units/modules from
+      marked files as blackboxes.
+
+ * Various
+    - Added support for $lt, $le, $gt, $ge to the code generating AIGs.
 
 Yosys 0.30 .. Yosys 0.31
 --------------------------

Makefile

@@ -141,7 +141,7 @@ LDLIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.31+49
+YOSYS_VER := 0.32
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -157,7 +157,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline f3c6b41.. | wc -l`/;" Makefile
+#	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline f3c6b41.. | wc -l`/;" Makefile
 
 # set 'ABCREV = default' to use abc/ as it is
 #