Yosys 0.47

Yosys 0.46 .. Yosys 0.47

• Various

  • Added cxxopts library for handling command line arguments.
  • Added docs generation from cells help output.

• New commands and options

  • Added "-json" option to "synth_xilinx" pass.
  • Added "-derive_luts" option to "cellmatch" pass.
  • Added "t:@" syntax to "select" pass.
  • Added "-list-mod" option to "select" pass.
  • Removed deprecated "qwp" pass.

• Verific support

  • Initial state handling for VHDL assertions.

WARNING

String attributes now have a distinct implementation from bit vector attributes, leading to often significant savings in runtime memory usage with up to 30% observed in real world designs.

Since both are represented with RTLIL::Const , its interface was changed. The bits member has been removed. To access any attribute as a bit vector, use the bits() method instead, which returns a const iterator. To modify a Const, you can call std::vectorRTLIL::State& get_bits() which forces the implementation to a bit vector. To get the number of bits, use the new Const::size() method instead of bits.size().

Yosys 0.46

Yosys 0.45 .. Yosys 0.46

• Various

  • Added new "functional backend" infrastructure with three example
    backends (C++, SMTLIB and Rosette).
  • Added new coarse-grain buffer cell type "$buf" to RTLIL.
  • Added "-y" command line option to execute a Python script with
    libyosys available as a built-in module.
  • Added support for casting to type in Verilog frontend.

• New commands and options

  • Added "clockgate" pass for automatic clock gating cell insertion.
  • Added "bufnorm" experimental pass to convert design into
    buffered-normalized form.
  • Added experimental "aiger2" and "xaiger2" backends, and an
    experimental "abc_new" command
  • Added "-force-detailed-loop-check" option to "check" pass.
  • Added "-unit_delay" option to "read_liberty" pass.

• Verific support

  • Added left and right bound properties to wires when using
    specific VHDL types.

Yosys 0.45

Yosys 0.44 .. Yosys 0.45

• Various

  • Added cell types help messages.

• New back-ends

  • Added initial NG-Ultra support. ( synth_nanoxplore )

Yosys 0.44

Yosys 0.43 .. Yosys 0.44

• Various

  • Added ENABLE_LTO compile option to enable link time
    optimizations.
  • Build support for Haiku OS.

• New commands and options

  • Added "keep_hierarchy" pass to add attribute with
    same name to modules based on cost.
  • Added options "-noopt","-bloat" and "-check_cost" to
    "test_cell" pass.

• New back-ends

  • Added initial PolarFire support. ( synth_microchip )

Yosys 0.43

Yosys 0.42 .. Yosys 0.43

• Various

  • C++ compiler with C++17 support is required.
  • Support for IO liberty files for verification.
  • Limit padding from shiftadd for "peepopt" pass.

• Verific support

  • Support building Yosys with various Verific library
    configurations. Can be built now without YosysHQ
    specific patch and extension library.

Resources

This is placeholder for build resources otherwise hosted on other places to make availability higher.

https://yosyshq.net/yosys/nogit/YosysVS-Tpl-v2.zip
https://www.zlib.net/fossils/zlib-1.2.11.tar.gz

Yosys 0.42

Yosys 0.41 .. Yosys 0.42

• New commands and options
  • Added "box_derive" pass to derive box modules.
  • Added option "assert-mod-count" to "select" pass.
  • Added option "-header","-push" and "-pop" to "log" pass.
• Intel support
  • Dropped Quartus support in "synth_intel_alm" pass.

Yosys 0.41

Yosys 0.40 .. Yosys 0.41

• New commands and options

  • Added "cellmatch" pass for picking out standard cells automatically.

• Various

  • Extended the experimental incremental JSON API to allow arbitrary
    smtlib subexpressions.
  • Added support for using ABCs library merging when providing multiple
    liberty files.

• Verific support

  • Expose library name as module attribute.

Yosys 0.40

Yosys 0.39 .. Yosys 0.40

• New commands and options

  • Added option "-vhdl2019" to "read" and "verific" pass.

• Various

  • Major documentation overhaul.
  • Added port statistics to "stat" command.
  • Added new formatting features to cxxrtl backend.

• Verific support

  • Added better support for VHDL constants import.
  • Added support for VHDL 2009.

Yosys 0.39

Yosys 0.38 .. Yosys 0.39

• New commands and options

  • Added option "-extra-map" to "synth" pass.
  • Added option "-dont_use" to "dfflibmap" pass.
  • Added option "-href" to "show" command.
  • Added option "-noscopeinfo" to "flatten" pass.
  • Added option "-scopename" to "flatten" pass.

• SystemVerilog

  • Added support for packed multidimensional arrays.

• Various

  • Added "$scopeinfo" cells to preserve information about
    the hierarchy during flattening.
  • Added sequential area output to "stat -liberty".
  • Added ability to record/replay diagnostics in cxxrtl backend.

• Verific support

  • Added attributes to module instantiation.