Yosys 0.35
Yosys 0.34 .. Yosys 0.35
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Various
- Improvements on "peepopt" shiftmul matcher.
- Improvements on "ram_style" attributes handling.
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Verific support
- Improved static elaboration for VHDL and mixed HDL designs.
- Expose "hdlname" attribute with original module name.
- Expose "architecture" attribute with VHDL architecture name.