info.yaml

# Tiny Tapeout project information
project:
  title:        "integer to posit converter and adder "      # Project title
  author:       "A. Fasolino, G.D. Licciardo, A. Torino, F. Del Prete, C. Parrella"      # Your name
  discord:      "andreafasolino_78028"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
  description:  "Our module executes a fixed to posit conversion and an addition"      # One line description of what your project does
  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
  clock_hz:     30000000       # Clock frequency in Hz (or 0 if not applicable)

  # How many tiles your design occupies? A single tile is about 167x108 uM.
  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

  # Your top module name must start with "tt_um_". Make it unique by including your github username:
  top_module:  "tt_um_afasolino"
  
  # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
  source_files:        
    - "add.v"
    - "data_posit_encoder.v"
    - "Fixed16toPosit16.v"
    - "LeadingZeroCounter_16b.v"
    - "normalizer_16.v"
    - "posit_top_open_hw.v"
    - "right_shifter_sticky_16.v"
    - "right_shifter_sticky_18.v"
    - "tt_um_afasolino.v"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
  # Inputs
  ui[0]: "data input"
  ui[1]: "data input"
  ui[2]: "data input"
  ui[3]: "data input"
  ui[4]: "data input"
  ui[5]: "data input"
  ui[6]: "data input"
  ui[7]: "data input"

  # Outputs
  uo[0]: "addition result"
  uo[1]: "addition result"
  uo[2]: "addition result"
  uo[3]: "addition result"
  uo[4]: "addition result"
  uo[5]: "addition result"
  uo[6]: "addition result"
  uo[7]: "addition result"

  # Bidirectional pins
  uio[0]: "data valid"
  uio[1]: "alu valid"
  uio[2]: "read data valid"
  uio[3]: "read data ready"
  uio[4]: ""
  uio[5]: ""
  uio[6]: ""
  uio[7]: ""

# Do not change!
yaml_version: 6