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Update Makefile
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afasolino authored May 30, 2024
1 parent 4f3e905 commit 88ec4f8
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2 changes: 1 addition & 1 deletion test/Makefile
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SIM ?= icarus
TOPLEVEL_LANG ?= verilog
SRC_DIR = $(PWD)/../src
PROJECT_SOURCES = tt_um_afasolino.v right_shifter_sticky_18.v right_shifter_sticky_18.v right_shifter_sticky_16.v posit_top_open_hw.v normalizer_16.v LeadingZeroCounter_16b.v Fixed16toPosit16.v data_posit_encoder.v add.v
PROJECT_SOURCES = tt_um_afasolino.v right_shifter_sticky_18.v right_shifter_sticky_16.v posit_top_open_hw.v normalizer_16.v LeadingZeroCounter_16b.v Fixed16toPosit16.v data_posit_encoder.v add.v

ifneq ($(GATES),yes)

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