0001-ARM-sun8i-h2-OPi-Zero-add-Sinara-Humpback-FPGA-confi.patch

From 088cca46c0713b62a08c7ba9ee15311380de4972 Mon Sep 17 00:00:00 2001
From: Etienne Wodey <wodey@iqo.uni-hannover.de>
Date: Wed, 24 Apr 2019 19:39:03 +0200
Subject: [PATCH] ARM: sun8i: h2+: OPi-Zero: add Sinara/Humpback FPGA config
 SPI port

This patch adds a gpio-bitbanged SPI port and the corresponding spidev
client for the OrangePi Zero board. The pinout matches the
configuration port for the FPGA flash configuration memory of the
Sinara Humpback carrier board.
---
 .../boot/dts/sun8i-h2-plus-orangepi-zero.dts  | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index 84cd9c061..ea673fbea 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -59,6 +59,8 @@
 		/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
 		ethernet0 = &emac;
 		ethernet1 = &xr819;
+		/* spi devices */
+		spi2 = &cfg_spi;
 	};
 
 	chosen {
@@ -111,6 +113,28 @@
 		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>;
 		post-power-on-delay-ms = <200>;
 	};
+
+	cfg_spi: spi2 {
+		compatible = "spi-gpio";
+		#address-cells = <0x1>;
+		ranges;
+		status = "okay";
+
+		sck-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>;
+		miso-gpios = <&pio 0 6 GPIO_ACTIVE_HIGH>;
+		mosi-gpios = <&pio 0 18 GPIO_ACTIVE_HIGH>;
+		cs-gpios = <&pio 0 10 GPIO_ACTIVE_LOW>;
+		num-chipselects = <1>;
+
+		spidev_cfg@0 {
+			compatible = "spidev";
+			reg = <0>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			spi-max-frequency = <1000000>;
+			status = "okay";
+		};
+	};
 };
 
 &cpu0 {
-- 
2.21.0