4 Jul 2020

test08b tries to implement a "pretty" pong. As it happens, I couldn't get the ball logic into XC9572XL, even with all the frills turned off.

Next steps (maybe for test08c):

Try to replicate simplicity of fpga4fun pong; it uses "wrong" timing that makes the logic simpler.
Try using lower resolution
Defining Xilinx GCK (global clocks) in Verilog is weird: Do it with a comment in the code. I did it here. XST sees this:
- In "HDL Analysis": Set user-defined property "BUFG = CLK" for signal <clk25>.
- In "Low Level Synthesis": implementation constraint: BUFG=CLK : clk25
Implement "swing" drift on the background.

test08c does work with different timing, and the TFT monitor I'm using can sync to it OK.