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11 Aug 2020

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So where to now? Maybe one of the following:

  1. Get GT's vgasim working in macOS (or Linux X Windows) for completeness.
  2. Do RAM hardware in current CPLD VGA thing. SRAM first. Later try DRAM?
  3. Try an experiment to implement a sprite. Optionally try to provide external register access to control it?
  4. Look more into bus sharing.
  5. Just try building an interface between CPLD and CPU with 7400-series tri-state buffers anyway, for the fun of it. e.g. 74LS244, or muxes, or AND arrays. Might need resistors to ensure bus contention is not fatal. Although, 74LS245 (bidi) might be fine, since CPLD can be in charge of OE.
  6. Examine ZX80 schematics to see how its video and CPU coexist. Consider other retrocomputers, too.
  7. Move to FPGA now?
  8. Stop doing VGA stuff; move back to NES board stuff?
  9. Any more Verilator to study? e.g. Nand2Tetris?
  10. Read Verilog book, and do other tutorials.
  11. Try doing something like a PPU, with a structure like RAM+ROM<=>CPLD<=>CPU.

Possible way to make video and CPU coexist on the same address/data bus. Let's assume a 6502:

  • CPLD hold the CPU in reset during normal visible rendering.
  • When the CPU comes out of reset, the CPLD needs to direct it to do something based on whether it's in HBLANK or VBLANK. This could be done by:
    1. CPLD feeding a specific reset vector to the CPU.
    2. CPU's reset handler reads something from the CPLD to work out what the current state is. Note that at 1MHz, a classic 6502 wouldn't be able to do anything during HBLANK: 800-640=160 cycles at 25MHz, which is less than 7 CPU cycles at 1MHz. During VBLANK, it would have:
    • (For 525 lines): 525-480=45, 45×800=36000 cycles at 25MHz, and at 1MHz this is 1,440 cycles; somewhere between maybe 240 instructions and 360 instructions, assuming about 4 clocks per average instruction.
    • (For 512 lines): 512-480=32, 32×800=25600 cycles at 25MHz, and at 1MHz this is 1,024 cycles; 170..256 instructions.
  • Instead of using reset, will RDY work on a 6502? See also: this

Instead of 6502, consider a Z80, or any CPU that verifiably has a way to do bus sharing. Related info about HALT and video here.