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24 Aug 2023

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raybox-zero: Improving the FSM

Next steps

  1. Get a cell/area count at 4x2 tiles before making any further changes. Try for these variations:
    1. 25MHz/new-OpenLane/SYNTH_STRATEGY=4
    2. 50MHz/new-OpenLane/SYNTH_STRATEGY=4
    3. 50MHz/old-OpenLane/default
    4. 50MHz/new-OpenLane/default -- should fail due to yosys-abc bug
    5. Repeat the above for 8x2 tiles too, because our design area might blow out in these subsequent steps.
  2. Repeat the above 5 (actually 8) steps for each of these following steps -- maybe in some of them, the yosys-abc bug will be hidden?
  3. Implement SPI access to pov, or even byte-wide access, because we need to see if this blows out the floorplan (e.g. by preventing logic reduction in the reciprocal and other multipliers). Assuming it's OK, implement use of it in the sim, too. DONE in 0135 -- it no longer fits in 4x2, but hopefully the improvements below will then help...
  4. Implement reciprocal sharing in wall_tracer, and prove that it works... i.e. both that make clean_sim still works as expected (hopefully also when pov is being sent rotated views), and that it can synth.
  5. Move height_scaler reciprocal into wall_tracer FSM.

Results from step 1 above

NOTE: These results are numbered per the variations above (with 5..8 being for 8x2 tiles instead of 4x2).

To respectively get:

  • cells_pre_abc, TotalCells, max speed
  • logic cells
  • utilisation and wires

...I run these 3:

summary.py --design . --run 0 --caravel --full-summary | egrep 'pre_abc|clock_freq|TotalCells'
./tt/tt_tool.py --print-cell-category | fgrep 'total cells'
./tt/tt_tool.py --print-stats

4x2 tiles

  1. Completes in 20:39 with success
    • cells_pre_abc: 18,675
    • TotalCells: 20,968
    • Max speed: 25.0MHz
    • Logic cells: 8,054
    • Utilisation: 51.99%
    • Wires: 265,305um
  2. Completes in 11:07 with setup violations
    • cells_pre_abc: 18,675
    • TotalCells: 20,933
    • Max speed: 40.8MHz
    • Logic cells: 8,046
    • Utilisation: 51.99%
    • Wires: 265,320um
  3. yosys-abc fails.
    • cells_pre_abc: 18,478
  4. yosys-abc fails.
    • cells_pre_abc: 18,675

8x2 tiles

  1. Completes in 17:37 with success
    • cells_pre_abc: 18,675
    • TotalCells: 35,823
    • Max speed: 25.0MHz
    • Logic cells: 7,990
    • Utilisation: 25.8%
    • Wires: 246,408um
  2. Completes in 11:49 with setup violations
    • cells_pre_abc: 18,675
    • TotalCells: 35,903
    • Max speed: 40.67MHz
    • Logic cells: 8,021
    • Utilisation: 25.8%
    • Wires: 246,738um
  3. yosys-abc fails.
    • cells_pre_abc: 18,478
  4. yosys-abc fails.
    • cells_pre_abc: 18,675

Note that I could previously get it to work when using the old OpenLane image (cb59d1f) and no SYNTH_STRATEGY=4 override, but it doesn't work anymore, probably due to a subtlety introduced from me needing to change unsized constants (e.g. from 0 to 1'b0).

Later

  1. Remove redundant map_rom. Note that this will require sharing the one remaining instance between map_overlay and wall_tracer. This probably means either delaying trace start until after the screen region where map_overlay masters it, or maybe pre-loading the current stripe of map_overlay data into registers...?
  2. Test that the design works on FPGA.
  3. Start thinking about TB.
  4. Work on sharing more resources, even if just where they can be spread out in the wall_tracer FSM, and see if this reduces cells/area.
  5. See if needStepX can just be replaced with a different state, or if there are other states we can merge for better cycle efficiency?