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0147-2023-09-27.md

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27 Sep 2023

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What next?

  • Been a while since I stopped hard work on stuff after completing the TT04 submission.
  • I did the VGA DAC PCB submission to JLCPCB yesterday.
  • Next thing I'd like to look at is related to TT05 and/or chipIgnite.
  • I should plan that Nov 19th to Nov 25th is YouTube video time.
  • I've got maybe 20 "normal" concentration days left of my leave.

High-level stuff to work on

  • Reading
  • Catch up on watching YT videos
  • Build TT05 project repo
  • Try putting texture loading (via SPI) into raybox-zero. Don't forget QSPI. What SPI hardware options do I have?
    • DE0-Nano EEPROM: only 2kb, i.e. 256 bytes? Adequate POC maybe but minimum texture is 32x32xRGB111 which is 3kb.
    • Pi Pico SPI sim (per RebelMike).
    • Do I have any SPI memories kicking around?
    • DE0-Nano has parallel-like SDRAM: Could we give it an external SPI-like interface?
    • Could my XC9572XL device be made to work as an SPI RAM? Remember Gisselquist Technology SPI controller (here?) and this one.
    • SD-card??
    • Plan also for SPI chip on TT motherboard??
  • Learn Pi Pico SPI controller coding.

Other notes

  • Formal verification: https://zipcpu.com/formal/2023/07/18/sdrxframe.html
  • Intel LPC (Low Pin-Count) interface could be handy for TT05?
    • SST49LF020 might allow 5-wire access but also parallel access inc. separate row and column parallel address multiplexing, which is interesting for map scanning.
    • I have some SST49LF008.

Work for today

  • Completed 0146 journal.
  • Went searching for SPI Flash ROM chips. Could only find some on ESP-01 boards.
  • Added some SPI flash memories to shopping carts in DigiKey and eBay.
  • Look into Uri's DFFRAM for TT05. This seems to use a specific RAM32 macro but it's not used by the GHA at this stage. Uri has more info near here. Even without RAM32, while set up as a 4x2, it uses a little over half this area.
  • Ways to access memory to read wall texture slices:
    • Use QSPI to read it all into a local buffer: 64x6 = 384 bits. Note that 1024 bits occupy 4x2 tiles, so 384 might occupy 3 tiles. I might just have this amount of space free in 4x2.
    • Consider using just 8 colours per slice (3 bits) with a palette: 64x3 + 8x6 = 240 bits: 2 tiles.
    • Select slice address bits in advance, then drive 6 parallel address bits (and read 6 bits) in realtime. In this case, an external memory can directly drive the RGB outputs.
    • Have a complex smaller buffer that knows which chunks of texture data to read in advance.
    • Have a complex external circuit which knows how to serve our needs.
  • It might be more realistic to work with a 2-bit sprite (3 colours + transparent): 128 bits, unless the 3 colours are also palette-mapped.