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0151-2023-10-03.md | 0153-2023-10-06.md |
- Implement test bench:
- Want to get a VCD to check SPI timing.
- Use iverilog, verilator, or cocotb?
- Try running cocotb on Windows? It needs iverilog too.
- When was the last time I wrote a TB and cocotb tests? Was it solo_squash? Examples:
- solo_squash:test/test_solo_squash.py
- tt03p5-solo-squash:src/test.py
- wrapped_rgb_mixer:caravel_rgb_mixer/test_rgb_mixer.py
- robojan's TT04 Tiny Breakout includes some nice tests in the
src
dir of the repo: tb.v; test.py; Makefile
- In Z2A, cocotb is introduced in part 2.1, and used again in 5.1
I've done this, and created Tip 2310A to describe the process.
I originally referred to the official iverilog on Windows setup guide but then found this Fandom page which shows how to compile on Windows (linking to a page with a lot more detail about doing this with MSYS2) but in the end it was just easier to use pacman
in MSYS2.
Just see my guide in 2310B for how to do this.
NOTE: Consider this superseded compared to steps I've now got in 0156.
- I'll use cocotb for now.
- In the project dir, create
test/
-- NO: TT convention is to place tests directly insrc/
- In there, create the testbench,
tb.v
. Main points:- Define inputs and outputs that we want the tests to have control over, giving them meaningful names.
- Have an
initial
block that specifies the$dumpfile
(in this casetb.vcd
). - Instantiate and wire up the design, calling it
uut
. In this case, it's thevga_spi_rom
module.
- Create a .venv for cocotb and these tests.
- Create
test.py
and fill it in -- more to come. - Create
Makefile
that uses cocotb -- more to come. - Write README describing how to set up everything and run the tests.
- Simulated
spiflash
inside a Caravel testbench - In Verilog, given an
assign
is like a direct wire/net connection, does it matter whether something is on LHS or RHS, if using simple direct signals rather than expressions?