| Previous journal: | Next journal: |
|---|---|
| 0163-2023-10-22.md | 0165-2023-10-24.md |
- tt05vsr can do QSPI. Not buffered yet, but generally works.
- raybox-zero can do QSPI textures now, rendering in full RGB222.
- texy.py updated to support raybox-zero's texture format.
- I was getting lots of noise problems when doing QSPI. I made a protoboard for the memory chip. This seemed to fix it for the AT25SF081B, but not completely for the BG25Q80. The problem sort of seems to be something to do with glitching (maybe ringing?) on SCLK.
- Add a logic switch to run different tests (quad mode) in the 2nd half of the screen.
- Don't worry about buffering for now. Just do direct quad IO output to screen.
- Map
in[2:0]to B, G, and R middle bits. - Map
in[3]to a left shift (brighten) for overall BGR111 value.
Per command 6Bh in datasheet, below is the sequence for AT25SF081B, and I think also Winbond W25Q parts, and probably most QSPI devices: 0. QE bit must be set. This can be programmed into the chip in advance. Other options exist, but out of scope. Hence this design assumes your SPI chip already has QE bit set automatically at power-on.
- Assert /CS, make sure io0 is set to OUTPUT.
- Clock in CMD[7:0] = 6Bh
- Clock in ADDR[23:0]
- (On falling SCLK edge of cycle 31 (CLK rising edge beginning cycle 32) switch io0 to INPUT.)
- Do 8 more dummy clocks
- Read then starts:
- For each even clock after that, chip should give us D[7:4] on io[3:0].
- For each odd clock after that, chip should give us D[3:0] on io[3:0].
- When we want to stop reading, release /CS, and io0 could probably just stay in INPUT mode since the next round will start with step 1 above again, when includes setting io0 back to OUTPUT.
- tt05vsr:
- CANCELLED: Change spi_out0 state checker to wrap line counter at 256 (so quad mode reads from address 0 instead of 256<<4).
- Recommend 1kΩ resistor in series with io[0] when initially testing on TT05 chip. This is because I don't have a proper reset, etc.
- Instructions should include mention of pre-setting QE bit, plus things to be wary of.
- Check io[3:0] VCD from cocotb simulation/tests, with
spiflashdisabled (allowing HiZ). - Replace
spiflashwith Winbond Verilog model, for cocotb purposes.
- raybox-zero:
- Option to use bitwise textures vs. texture SPI chip.
- Map memory (i.e. simple local map memory we can edit via SPI).
- SPI reg editing of higher texture addresses, and possible mapping of texture addresses?
- Implement SPI reg access via PicoDeo (needs de0nano TOP updated to wire up SPI reg signals)
- Colour format used by raybox-zero is currently bgrxBGRx where 'x' is unused, lowercase is LSB of each colour channel, and uppercase is MSB. I call this '2bgrx' in texy.py.
- What happens if you try to do QSPI Quad Fast Read command 6Bh without QE bit enabled? Does it still output data with 4-bit alignments, but only MISO is valid? Or does it output nothing? Something we can test...
- How realistic is it to do DisplayPort with only 50MHz bandwidth?
- Can we do 1920x1200 resolution or 1920x1440 over VGA cable?
- 1920x1200@60Hz: All timings are evenly divisible by 8 (not 6). HSYNC is neg, VSYNC is pos. 193.16MHz div-8 is 24.145MHz. At div-8, on-screen pixels would be 240. If we start stored-mode at 192, we have 132 clocks (plus a little wrap-around onto the next line, if we want it, but that needs smarter state counting).
- 1920x1440@60Hz: All timings are evenly divisible by 8 (not 6). HSYNC is neg, VSYNC is pos. 234.0MHz clock div-8 is 29.25MHz. At div-8, on-screen pixels would be 240. If we start stored-mode at 192, we have 133 clocks (plus a little wrap-around onto the next line, if we want it, but that needs smarter state counting).