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0192-2024-02-02.md | 0194-2024-02-05.md |
TODO: Put in scope screenshots, etc.
- First make sure I can measure current with my scope.
- I used my RP2040 bodge-soldered test board with USB power.
- Put a 1Ω resistor on the low side of the USB power (i.e. in series between USB GND and DUT GND).
- If we expect up to 200mA load from RP2040:
- 200mA thru 1Ω is scope-measured voltage (V=IR) of 200mV, hence ~4.8V reaching the 3.3V regulator.
- Power thru resistor is (P=VI) 40mW, so fine for a 1/4-watt resistor.
- This seems to work. Idle(ish) current looks to be in range of 10~20mA, with some periods of activity around 40mA.
- Testing VSS pins (and EP):
- All VSS pins (1, 10, 20, 23, 29, 38, 39, 52, 56) appear shorted.
- I was getting a 'diode' reading of 1.403V forward from EP to each VSS pin, and 1.695V reverse for each. I was also getting resistance measurments of 6~9MΩ. This is interesting because in my early testing before soldering I was getting nothing at all.
- Testing power pins:
- All VCC (?) pins (9, 17, 18, 30, 40, 47, 49, 63, 64) appear shorted.
- Try applying raw power directly to any VCC+VSS pin pair, and measure current:
- I've observed that typical current directly at 5V from USB is about 5mA, with some predictability where it pulses at ~10mA.
- It seems to move onto some bursts between 6~12mA with some evidence of oscillation -- hard to tell but on the order of 300kHz up to maybe 1.5MHz. Could be due to random start-up state of the DCO/DLL.
- SPI flash CLK seems to hover around 1.6V
- Put in required 100nF decaps, then join all respective power and GND (plus EP) pins:
- NOTE: I think doing caps first made it easier because they gave a foundation for where the wire would run.
- I used 30 AWG single-core PTFE (Teflon) coated wire, i.e. wire-wrap wire, to do point-to-point soldering.
- My iron was set to 450°C; hot enough to rapidly break down the PTFE, but maybe too hot? I avoided contact for too long, but it's possible there might've still been too much heat creeping into pins of the ASIC... hopefully not, though, and hopefully these are just large nets anyway, inside.
- I tested afterwards to make sure there were no unintentional shorts.
- Put in headers (I'll go with stackable).
- Try powering up, just via any power pair (e.g. VCC on 9, VSS on 10).
- First 1.5ms~2.5ms, consuming ~20mA.
- Then mostly stable at about 15mA.
- On a really long timebase, I was able to touch bare pins (esp. near
clock
) and I think I observed that it was picking up a 50Hz hum as the clock, which was then coming back out viaflash_clk
(pin 25) for a while. - After pulling
resetb
low and then releasing it again (with a simple jumper wire), I could seeflash_clk
andflash_io0
being asserted in what looked like a read cycle (SPI command 0x03). - It looks like it went thru 288
flash_clk
cycles before halting, which comprises 32 for READ command and address, then 256 bits of data (32 bytes).