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30 Mar 2024

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TT04 raybox-zero test prep

  • Still very busy as I prepare to start officially with Efabless next week.
  • TT04 chips have come back and are with tnt.
  • tnt could do some basic tests even just with oscilloscope so I'll work on preparing helpful instructions for that.

TODO

  • Need to prepare proper instructions for structured testing/debugging anyway.
  • I've added to some of the hardware stack for my DE0-Nano FPGA devboard, so I need to document that and make sure both the raybox-zero/de0nano target still works correctly with it, and which GPIO signals are required for normal operation now. See 0194 and actual current GPIO-1 pinout.
  • Document raybox-zero versions in README, and how they relate to tt04-raybox-zero
  • Work out which are the latest versions of raybox-zero (e.g. GFMPW1 version) but also find which version was submitted to EW
  • Check which versions can be run in Verilator & Quartus. Fix if required.

Anton's current DE0-Nano GPIO-1 pinout

Below are all the connections that I have on my GPIO-1 header right now, though not necessarily all of them are used for all raybox-zero versions.

NOTE: The below RGB333 DAC pinout is only used by raybox-zero/de0nano target if `define RGB3_DAC is used (and it typically is), in which case R0, G0, and B0 are all unused (off), and only the upper 2 bits of each colour channel are driven by the design...

  ______________________+-----+-----+_________________________________
 /(ROM pin 6) SCLK O  40|io33 |io32 |39    (NC)                       \
|                       +-----+-----+                                  |
|             (NC)    38|io31 |io30 |37 I  io3 (ROM pin 7)             |
|                       +-----+-----+                                  |   BOTH sides are for
| (ROM pin 3)  io2 I  36|io29 |io28 |35 IO io0 (ROM pin 5) (MOSI)      |   SPI ROM module:
|                       +-----+-----+                                   >  Newer versions of raybox-zero
|             (NC)    34|io27 |io26 |33 I  io1 (ROM pin 2) (MISO)      |   use this for texture ROM.
|                       +-----+-----+                                  |   NC for older versions
| (ROM pin 1)  /CS O  32|io25 |io24 |31    (NC)                        |   (e.g. 1.0, 1.1, 1.2)
|                       +-----+-----+                                  |
| (ROM pin 4)  GND -  30| GND |VCC3 |29 +  VCC3P3 (+3V3) (ROM pin 8)   |
 \______________________+-----+-----+_________________________________/
            hblank O  28|io23 |io22 |27 O  vblank 
                        +-----+-----+
                K3 I  26|io21 |io20 |25    (NC)
                        +-----+-----+
                K2 I  24|io19 |io18 |23    (NC)
                        +-----+-----+
              (NC)    22|io17 |io16 |21    (NC)
                        +-----+-----+
--------------(NC)----20|io15 |io14 |19----(NC) <-----(these 2 pins blocked by VGA DAC plug-in PCB below)
  ______________________+-----+-----+_________________________________
 /   (unused:0) G0 O  18|io13 |io12 |17 O  B0 (unused:0)              \
|                       +-----+-----+                                  |
|               G1 O  16|io11 |io10 |15 O  B1                          |
|                       +-----+-----+                                  |
|               G2 O  14| io9 | io8 |13 O  B2                          |
|                       +-----+-----+                                  |
|              GND -  12| GND |VCCS |11 +  VCC_SYS (+5V)               |
|                       +-----+-----+                                  |   BOTH sides are for
|            HSYNC O  10| io7 | io6 |9     (NC)                         >  VGA RGB333 DAC module
|                       +-----+-----+                                  |   with K1/K4 buttons
|            VSYNC O   8| io5 | io4 |7     (NC)                        |   on IN0/1 respectively.
|                       +-----+-----+                                  |
|    (unused:0) R0 O   6| io3 | io2 |5     (NC)                        |   NOTE: All of these pins
|                       +-----+-----+                                  |   are populated in my header
|               R1 O   4| io1 | IN1 |3  I  K4                          |   as long pass-through pins
|                       +-----+-----+                                  |   so they can be used
|               R2 O   2| io0 | IN0 |1  I  K1                          |   for other purposes.
 \______________________+-----+-----+_________________________________/
                                   \
                                    PIN 1 of GPIO1 header.

The K1..K4 buttons are active-high. They are pulled low by 22k resistors when open,
and pulled high by 100R when pressed.

The system clock is provided by the DE0-Nano's CLOCK_50 (50MHz) and is divided by 2 to make the typical
25MHz VGA clock.

The DE0-Nano's KEY[0] provides the reset signal.

I've updated the main branch of https://github.com/algofoogle/raybox-zero so that the de0nano target now matches the above new pinout, and tested it on the hardware.

This update is tagged 1.2.

Figuring out which versions are which

  • 1.0 (main branch):
    • Actual version submitted to TT04.
    • SPI for POV.
    • SPI2 for 'registers', supporting: FLOOR, SKY, LEAK
    • inc_px & inc_py inputs for demo
    • H/VBLANK outputs
    • de0nano target assumes RGB111 VGA adapter
    • Sim make csr works; constantly 'animates' FLOOR/SKY/LEAK (no option to turn it off).
  • 1.1 (main branch):
    • Adds OTHER to SPI2
    • de0nano target updated to use RGB333 VGA DAC by default
    • Sim make csr works as per 1.0
  • 1.2 (main branch):
    • Fix for different Q values
    • Adds VINF to SPI2
    • Sim timing is now adaptive; adds optional MouseY=>TexV slide; \ toggles VINF; / toggles SPI2 'animation'.
    • de0nano target updated for newer GPIO-1 pinout (compatible with TT03p5 too).