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16 Aug 2024

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Completed csdac_nom initial layout for tt08-vga-fun

As of commit 57c6665 I've got a completed initial layout for csdac_nom:

csdac_nom initial layout

It seems to be DRC clean and fractionally smaller than 57x60um. To my surprise, LVS passed on the first go:

$ PROJECT_NAME=csdac_nom make clean lvs
...
Contents of circuit 1:  Circuit: 'csdac_nom'
Circuit csdac_nom contains 28 device instances.
  Class: sky130_fd_pr__nfet_01v8 instances:  25
  Class: sky130_fd_pr__res_high_po_5p73 instances:   2
  Class: sky130_fd_pr__pfet_01v8 instances:   1
Circuit contains 29 nets.
Contents of circuit 2:  Circuit: 'csdac_nom'
Circuit csdac_nom contains 28 device instances.
  Class: sky130_fd_pr__nfet_01v8 instances:  25
  Class: sky130_fd_pr__res_high_po_5p73 instances:   2
  Class: sky130_fd_pr__pfet_01v8 instances:   1
Circuit contains 29 nets.

Circuit 1 contains 28 devices, Circuit 2 contains 28 devices.
Circuit 1 contains 29 nets,    Circuit 2 contains 29 nets.


Final result: 
Circuits match uniquely.
.
Logging to file "lvs.report" disabled
LVS Done.
LVS OK

Features of the layout include:

  • Positive and negative (i.e. inverted) digital inputs (8 bit pairs) across the top, on m1.
  • vcc and vss ports in the top-left, on m4. These branch out on m4 and m3, and are typically all 1um wide where they carry current -- should allow up to about 1.5mA (where we only need 0.5mA).
  • Analog output ports in the bottom-right corner. Probably only Vneg will be used but there's also its complement (Vpos) and the bias voltage (Vbias) for the current-source transistors.
  • Vbias reference generator is the pair of transistors in the top-left corner.
  • Left-hand half, from top to bottom, is triplets of transistors that steer current for bits 7, 6, 5, 4, and 3.
  • Right-hand half, from top to bottom, is the same for bits 2, 1, and 0. NOTE: Because these are very LONG transistors (as opposed to wide), they are rotated 90° compared with the left-hand column, and in this case I've got the Vbias m1 strap going across the channel. Not sure if that's a bad idea.
  • Big pull-up resistors on the right for each of Vpos and Vneg. These need to be this large for current capacity, i.e. I want to keep them under the 100uA/um recommended limit, and these are 5.73um wide (thus 573uA gives enough headroom).

Extraction and simulation

PROJECT_NAME=csdac_nom make csdac_nom.sim.spice

This produces mag/csdac_nom.sim.spice with a large number of parasitic resistors and capacitors, as expected. To my surprise, the port order is sensible (even though the port numbers are odd in the .mag file):

.subckt csdac_nom_parax p0 n0 p1 n1 p2 n2 p3 n3 p4 n4 p5 n5 p6 n6 p7 n7 vcc vss Vpos Vneg Vbias

Back in xschem/ I copied tb_csdac.sch to tb_csdac_nom.sch and edited it to specifically use csdac_nom (rather than the parametric version, csdac). I also copied csdac.sym to csdac_nom.sym and fixed that up to make it an easy drop-in.

Create a 2nd copy of the main DUT schematic, name its outputs to include _pex as a suffix, then edit the 2nd instance (that will represent the layout/parasitic-extraction version) to include:

schematic=csdac_nom_parax.sim
spice_sym_def="tcleval(.include [file normalize ../mag/csdac_nom.sim.spice])"
tclcommand="textwindow [file normalize ../mag/csdac_nom.sim.spice]"

I adjusted the graph a little (taking out Vpos) and the performance seems pretty consistent, though Vbias_pex is a little flat, meaning less current through the transistors:

Next steps

Digital block and integration

The 3v3 1x2 TT layout is 136.14um x 225.76um. For some reason there's an extra region on the RHS that is unusable but visible. I don't know what that is.

Usable area in the layout is probably about 125x215um.

The remaining usable area for a digital block would be about 125x145um:

If I needed more, I could forget the 3v3 experiment, or go for 2x2 tiles.

I can't remember what hardening size I got to for my updated Verilog (inc. improved features, line debug, etc.). It might've been this from 0205 (2024-05-30); if so, I got a 117x117um harden apparently.

Ah, it's obvious why it had to be a lot smaller originally: https://github.com/algofoogle/tt-vga-fun/blob/main/docs/info.md -- the RDACs dominate.

Other stuff

Other possible improvements

  • Digitally switch different Vbias levels, or even make Vbias an INPUT driven by another circuit (e.g. differently-sized current reference resistors that can be switched).
  • Go back to Xschem and see if we can fix the imperfect balancing of the current transistors.
  • Option to switch different pull-up resistors (or just turn them off and do an external pull-up).